JPS6187452A - Ring network for communication between one chip processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

BACKGROUND OF THE INVENTION This invention relates to a ring network for communication between one-chip processors having a serial transmitter and a serial receiver.

Generally, there are three different ways to grant transmission rights in a given network. ET, HERN,
ET is the so-called CSMA/CD method (carrier
5ense ＋＊ultiple accesswit
h collision detection).

All processors have equal priority, ARC
NET uses a so-called token pass method. Here, the right to transmit is from one processor to the next.
When the right to transmit is lost, complicated procedures are required to determine a new active processor. IBM
In the ring, data is circulated within the ring, and transmission rights are transferred using a token pass method. In the known low power networks and their variants a, at least one network controller, line driver, sometimes code converter and FI as an additional IC unit are required to connect a one-chip processor.
fo intermediate memory is required. The applicant has already described in German published patent publications No. 3313240, No. 3333847 and US patent application no. We have disclosed a local network that allows you to connect to that network just by using it. Each one-chip processor can operate independently as one local processor and as an interrupt mechanism controlled as a network controller.

&riΩto1 One object of the present invention is to use a plurality of one-up processors having a serial transmitter and a serial receiver as independent local processors, or to use the CSMA/CD method and tokens via a network driver and a ring network. The object of the present invention is to provide a circuit means to enable operation as an 11-inclusive mechanism controlled as a network controller that communicates by a path method.

Another object of the invention is to provide a means for operating a one-chip processor in communication over a ring network.

Yet another object of the present invention is to provide a ring network with M simple structure and very flexible operation for communication between one-chip processors.

These objects are achieved by a ring network for communication between a one-chip processor having a serial transmitter and a serial receiver, and this ring network is composed of the following means.

One ring transmission line, used for each processor, selectively couples the transmitter or the receiver to the transmission line, and allows the signal in the ring transmission line to pass when the one-chip processor does not have the right to transmit. a1@; a plurality of network driver circuits for each of said one-chip processors to selectively operate said one-chip processors as independent local data processors or network controllers based on a predetermined prioritization scheme; a control means installed in the network driver circuit; a first tristate control means installed in the network driver circuit and connected to the ring transmission line;
line driver; having an input connected to the output of a transmitter of a one-chip processor, for passing a serial data word from the transmitter to the ring transmission line; 'A of signal 1
a timing circuit for use in each one-chip processor, having the function of blocking 11 errors and being triggered by a start bit generated by said transmitter;

In a preferred embodiment, the signal reaching the ring transmission line is amplified by an amplifier and then supplied to a receiver of a one-chip processor and a noise filter consisting of another amplifier, resistor, and capacitor. The noise filter uses a tri-stay that has a feedback mechanism and a function to always pass this signal to the ring transmission line when the transmitter of the one-chip processor is not triggered by a monoflop) (
(Lristate) Noise is suppressed by making the arrival signal hc before it is applied to the line driver. When the monoflop is triggered by the start bit of the transmitter, the serial data word following the start bit is activated by the monoflop on behalf of the tristate line driver to transfer the data word to the ring transmission line. It is passed through a second tristate line driver to transmit. Supply of two-way work driver'II1.
When the voltage falls below a predetermined value, the two tristate line drivers are switched to the third mode of operation by the supply voltage detector, and the network driver is fully shunted by the enhancement FET transistor or relay. be done. The termination resistor of the ring transmission line is an enhancement FET to suppress unnecessary attenuation.
It is sufficiently blocked by the transistor. When the ring network is loaded, the transmission of the right to transmit is accomplished by the one-chip processor that has completed the data transmission resetting the right to transmit bit or flag and issuing some information, preferably by issuing an address 255 to indicate that the right to transmit is granted. This is done by communicating 92 what is granted in the next data byte 255 to all other one-chip processors, which are then received by all one-chip processors via the attached network driver and ring network.

In contrast, subsequent data bytes 255, which are responsible for the actual transfer of the transmission right, are passed in sequence through the ring network to the next one-chip processor ready for transmission. Meanwhile, the remaining one-chip processors that are ready to transmit continue to have transmission rights transferred from the first one-chip processor into the ring network by the attached network driver to prevent data bytes 255 from being recirculated. Therefore, at the same time as it receives address 255, it transmits its next data byte 00 in synchronization with this. In this way, only the next one-chip processor whose transmit request flag is set receives the right to transmit in response to data byte 255, and at this time resets the transmit request flag and sets the transmit right flag. In this way, the next data transmission of this one-chip processor is started.

No other one-chip processor that is not ready to transmit, that is, has reset its request-to-send flag, will receive the data byte 255 and gain the right to transmit, unless there is no one-chip processor to take over the right to transmit.
Unless the first one-chip processor is programmed to continue transferring its transmission rights cyclically until another one-chip processor picks up the transmission rights, it becomes dormant.

In order to optimize data throughput in a ring network, it is conceivable to direct the granting of transmission rights at the time of network rotation. By the way, the ring network uses CSMA/CD when starting up and stopping transmission.
method to recover its transmission activity.

At this time, all one-chip processors have the same priority, and if there is a transmission request from one or several one-chip processors in the ring network before the ongoing data transmission is completed, the right to transmit is granted. Transfer is performed using the token pass method. The one-chip processor then transfers the right to transmit to the next succeeding and ready-to-send one-chip processor on the ring network.

The token pass method applies as long as the ring network is loaded. On the other hand, after the ring network is loaded, the transmission right is granted manually using the CSMA/CD method.

A significant advantage of the invention is that it requires only one network driver as an additional IC unit to connect a single chip processor to a ring network. Since this is unidirectional data transmission within the ring network, and No. 0 is refreshed at the connection point of each one-chip processor, the transmission distance can be long. Optical transmission lines can also be used.

Preferred specific example of each of the ring networks shown in Figure 1-1! ! The iI element has four constituent units: one-chip processor 1,
A one-chip processor comprising a driver 2 and means, preferably e.g. family: Intel's 8044.8051.8096, Motorola's 6801
, Rockwell's 6500/11 or 6500/13, or Mosnaq's 68200. This one-chip processor can not only operate as a network controller with control of the interrupt mechanism, but also as a local computer. It is also programmed to perform the following functions.

Data transmission within the ring network is unidirectional. That is, each path 17 connects a serial operation transmitter of one-chip processor 20 to a serial operation receiver of one-chip processor 21. At each connection of the network, ie each network driver 32.
At 37 (Iff12), the serial message is refreshed. Therefore, the ring network consists of a coaxial transmission path, a parallel transmission path (Twinax tran
1nes), it is possible to transmit data over long distances using optical communication channels. Data transmission is preferred.

NRZ code, NRZI code or two-phase code (b
iphag@code).

The two functions of network driver 2 are to pass 1 the one-chip processor l attached to network driver 2.
7 and closing the path 17 in a ring shape. This network driver maintains vL control over the network even when none of the one-chip processors are ready to transmit, and even when each network driver's power supply is down. Specifically, the signal arriving at the ring path 17 is amplified by the amplifier 2, and is passed through the noise filter 3 to suppress noise.
, the signal is delayed by a predetermined time, and the signal is supplied to the tristate path driver 6.
The signal is fed to the next part of the ring path 17.

This closes the ring network connection. This ring is completely closed without any transmission. The noise filter 3 is constructed by shunting an amplifier 3' and a capacitor, and has a resistor 5 connected to its input.

The network driver 2 is connected to the ring path 17 through the amplifier 2 of the serial receiver 10 of the one-chip processor 1, so that the one-chip processor is in a "listening" state for the ring network at any time. .

It is completed as disclosed in our company's West German Patent Publication No. 3213240.2.

When the start bit logic signal 0 of the serial data byte output by the transmitter 11 is triggered to the monoflop 9, the monoflop 9 triggers the tri-state (tr
istat 14) The path driver 8 uses the ring path 17 for the data word or byte and the following pause time.
The transmitter 11 of the one-chip processor I is connected to the transmitter 11 of the one-chip processor I.

During this time, the tristate path driver 6 is driven by the monoflop 9 into the tristate l-(
(tristate) mode. This therefore connects the one-chip processor l, in particular its transmitter fall, to the ring network. Only the one-chip processor l decides which of the two rings to close by means of the serial transmitter 11. This means that one of the two path drivers 6 and 8 is tristated by the monoflop 9.
This is done by selectively switching to the mode.

Additionally, network driver 2 includes a supply voltage detector 14 that switches both path drivers 6 and 8 into tri-state (tristaLe) mode if the operating voltage drops below a critical value. A supply voltage detector 14 is used to keep the ring network active even if one network driver drops out.
The depletion F connects the two parts of the ring path 17 by FET transistors 12 and 13, and the enhancement F disconnects the termination resistor 16 by cutting off the FET transistor 87 to avoid unnecessary attenuation, which is Connection of ring path 17 and terminating resistor 1
6 is done by an external relay controlled by a supply voltage detector 14.

According to an important feature of the invention, the transfer of the transmission rights of the active one-chip processors 20 is done using a token-passing scheme when the network is loaded according to FIG. As a result, only the one-chip processor 22 located at the 0th order that is ready to transmit requires an indication to ask the other one-chip processors 21 to 27 whether or not to take the transmission right. The chip processor 22 must remove the necessary indications to take the transmission right from the next one-chip processors 23-27.

For this purpose, an indication or flag for transferring the transmission right must be stored and removed within an additional operating time.

If the indication or flag were to be removed before leaving the network driver, this would increase the operating time of the network driver 2 and result in a significant reduction in transfer efficiency. In order to avoid this process, according to FIG. 2, the one-chip processor 20 transferring the transmission right transmits two characters in succession, e.g.
Address 255 is signaled 51 to all chip processors 20-27 in the token ring network, and transmission rights are newly assigned by associating with the next data byte 255. Therefore, one-chip processor 20
, having completed its data transmission, cancels its own transmission rights. This transmission, address 255, is received by all one-chip processors 20 to 27 connected to the token ring network through network drivers 31 to 37. The two one-chip processors 20 to 27 pass through each network driver 31 to 37 the following data bytes 255.
This is because the one-chip processor 22, 24, 26 that is preparing for the transfer will pass through the network driver 32, 34, 36 the data bytes 255 of the one-chip processor 20 in the ring network. In order to prevent this, as soon as the address 255 is received, each different data byte sequence, for example 00, is automatically transmitted in synchronization therewith. By this operation, the one-chip processors 22 and 24 that sent
．． Since the transmission request flag of 26 is set,
Only one-chip processor 22 following processor 20 receives the right to transmit with data byte 255. By setting the transmission request flag, the transmission request flag is cleared and the transmission right flag is set. therefore,
Data transmission begins from the one-chip processor 22 that started first. One-chip processor 21 also receives data bytes 255. However, since the request to transmit bit is not set, acceptance of the right to transmit will be skipped. One-chip processor 20 to 27
If none of the one-chip processors 2θ receives the transmission right, the one-chip processor 20 cyclically accepts the transmission right until one of the one-chip processors 2θ to 27 receives the transmission right. If it is not programmed, transmission will be suspended.

In a loaded network, transmission rights are transferred by a token-passing method. Therefore, in a conventional network, the right to send is transferred regardless of whether the next processor is ready; in a ring network according to the invention, the right to send is transferred when another processor is ready. Ru. Therefore, unnecessary waiting times do not occur.

Suppose that the one-chip processor 21 transmits,
Initially, the processor sets a send request flag. In the loaded network, when each transmission right transfer announcement is made, it is checked whether this one-chip processor 21 is the next one. If applicable, the previously submitted transmission request of this one-chip processor 21 is executed.

When the network is not transmitting, the one-chip processors that wish to transmit will try to gain access to the network with equal priority according to the C8ME/CD scheme.

This is done by checking the ring path availability of the one-chip processor. Access is done statistically and varies over time by a one-chip processor. If a transmission collision occurs between two or more one-chip processors, the transmission collision between these one-chip processors
As soon as a one-chip processor gains access to the ring network without collision, it resets its request-to-send flag and sets its right-to-send flag. In this way, one A chip processor gains priority over all other one-chip processors until the transmission is complete.

These one-chip processors that compete with the one-chip processor that has gained access to the ring network receive their transmission rights one after another in the loaded network according to transfer based on token-passing rules.

Transmission collisions are detected within the ring network without a collision detector. This is due to the one-chip processor receiving the data bytes sent along the ring network. Accesses of one or several one-chip processors lead to transmission collisions if there is no concurrency between received data bytes and transmitted data bytes with the same priority.

The protocol of this ring network is based on the invention corresponding to German publication No. 3333847.7. Fig, 3
a consists of the following = IJ address 40.
Source dress 41. Command 42. Receiving address 43° Sending address 44. Number of data bytes: 45. data bytes and their checksums, identification
tion) Notch X-/K sum 47, data byte 47 divided into 15 data bytes, checksum 46 and stop byte 48, data byte 47 divided into 15 data bytes, checksum 46 and stop byte 48. Acknowledgment (acknowledge + 5ent) or response transmission right by a 3-bit command. is transferred to the receiver and returned to the requesting transmitter upon completion of the data transmission, 42 informing the transmitter and receiver of which address the transmitter or receiver is valid for internal or external data memory. and acknowledge receipt of the received data.
nt) indicates which of the data responses is dominant.

Fig. 3a shows a protocol without receipt confirmation or response. Fig. 3b shows a data transmission protocol with an edit mark or receipt confirmation from the receiver 49 added to Fig. 3a. Receipt confirmation is the next reception. Achieve the goal by address or frog first sending address. Fig
, 3c, the receiver sends the transmitter 50
mark or character that requests the transmitter to send data. The receiver 51 data message is appended to the transmitter 50 request.

Data protection consists of marks or characters and data parts (dat).
(a portions) D) This is done by successively sending a checksum. The transmitter adds characters and/or data and sends a checksum when the number of remaining data bytes to be sent still corresponds to XOH. The receiver digitizes the received characters and/or data, enumerates the remaining fiXOH, and checks whether the checksum corresponding to the received data is equal to the received checksum. If the checksums do not match.

For example, if there is one more byte, that byte is not received and is returned to the transmitter. In the case of a wide range transmission characterized by a destination address of 0, the receiver returns neither received bytes nor conflicting bytes.

Regarding transmission errors, these are detected by the transmitter as the received bytes are compared to the transmitted ones. When a transmission error is detected, the transmitter attempts to correct the error. This is a new proof (identif
ica-tion) and the last data part (dat
This is done by resetting and starting the transmission request, which is the result of repeated a por-tion). The last 8 bytes are repeated for safety reasons and the allowed branching path lengths. The receiver waits until the transmitter starts transmitting data again.

If the network controller in the one-chip processor is implemented in hardware rather than software, the serial data transmission speed no longer depends on the processing speed of the one-chip processor, but increases. Additionally, data transmission to internal or external data memory is DMA
(Direct Memory Access) 7 accesses allow a one-chip processor to perform this without affecting the ring network.

The magnitude of the delay of the signal on the ring line due to the nozzle filter is such that the one-chip processor 20 uses only address 255 as a mark to transfer communication rights, and the addressing bits are passed from the network driver through the tri-state line driver. So that the succeeding one-chip processors 24 and 26 can complete preparations for transmission before the message is sent.

Tri-state driver 8 of network driver 32
controls the addressing bits at address 255 by (
It is necessary to choose which one to suppress.

The network driver 2 is usually a separate IC unit, but is preferably integrated within a single-chip processor l.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a network driver used in a preferred embodiment of the ring network of the present invention. FIG. 2 is a block diagram of a network driver for explaining transmission right transfer, and FIG. I will show you the protocol. Patent applicant: Siegfried Schwartz, patent attorney, Shuhei Matsuoka Procedural amendment (voluntary) August 1985 236 1. Indication of the case 1985 Patent Application No. 163789 2. Name of the invention One-chip processor-to-processor communication Relationship with the person making the amendment 1'19 Patent applicant Siegfried Schwartz 4, agent 1-9-5 Kudan Kita, Chiyo 16-ku, Tokyo 102 Asa Kudan Apartment No. 302 5, Specification subject to amendment 8 (clean/no change in content) Procedural amendment (method) % formula % 2. Name of the invention Ring network for communication between one-chip processors 3. Relationship with the person making the amendment Patent applicant seek Fleet Schwartz 4, Agent Address: 302 Asahi Kudan Mansion, 1-9-5 Kudan Kita, Chiyoda-ku, Tokyo 102

Claims (25)

[Claims] (1) A ring network for communication between one-chip processors, each having a serial transmitter and a serial receiver, consisting of the following: One ring transmission path, used by each processor, and each with a selected a plurality of network driver circuits having the function of automatically coupling the transmitter or the receiver to the transmission path and passing the signal in the ring transmission path when the one-chip processor does not have the right to transmit; a predetermined priority; control means installed in each of said one-chip processors for selectively operating said one-chip processors as independent local data processors and/or network controllers based on a ranking scheme; a first tristate line driver provided and connected to the ring transmission line; having an input connected to an output of the transmitter of a one-chip processor to transmit serial data words from the transmitter to the ring transmission line; used in each one-chip processor, having the function of passing a transmission line and blocking the passage of the signal in the ring transmission line, and being triggered by a start bit generated by the transmitter. timing circuit. (2) A second tri-state driver for selectively transmitting signals in the ring transmission path when the timing circuit is not operating.
Ring network described in ). (3) if an excessive drop in supply voltage is detected, blocking the first tri-state line driver so as to transmit the signal in the ring transmission path essentially without attenuation; Ring network according to claim 1, further comprising a supply voltage detector for the generation of a blocking signal that shunts the driver. (4) The network driver has an input connected in series to the ring transmission line, an output connected to the receiver and the input of the noise remover, and the output of the noise remover is connected to the second try. 2. The ring network according to claim 1, wherein the second tristate driver is connected to an input of a state driver, and the second tristate driver is connected in series to the ring transmission path. (5) The ring network according to claim (4), wherein the noise remover is configured by a series connection of a resistor and an amplifier shunted by a capacitor. (6) The ring network according to claim (1), wherein the timing circuit is a monoflop. 7. The ring network of claim 3, wherein said network driver is shunted via switching means operable by said blocking signal generated by said supply voltage detector. (8) The ring network according to claim (7), wherein the switching means is a FET transistor. (9) The ring network according to claim (1), wherein the priority assigning method is a CSMA/CD method. (10) The ring network according to claim (1), wherein the priority assigning method is a CSMA/CD method. (11) The ring network according to claim (1), wherein the priority assigning method is a token pass method. (12) Claim No. 1, wherein the priority assigning method is a combination of a CSMA/CD method and a token pass method.
) term ring network. (13) When the control means including the one-chip processor completes the data transfer, the one-chip processor receives the transmission right and is ready for the next first transfer.
The ring network according to claim 1, wherein the ring network is transferred to a one-chip processor that becomes a one-chip processor. (14) In transferring said transmission right from a one-chip processor, that processor first issues an announcement that is received by all one-chip processors, while
The information following the announcement is received only by the next succeeding one-chip processor that is ready to request transmission, and that processor blocks the transmission of said information to other than said one-chip processors. No. (
13) Ring network described in section 13). (15) The ring network according to claim 14, wherein when the next one-chip processor receives the information, the transmission request flag is reset while the transmission right flag is set. (16) A ring network operation method for communication between one-chip processors consists of the following steps: a) Providing a ring transmission path; b) Transferring the transmission right to the first one-chip processor that has completed the transfer. to one of the one-chip processors next to the first one-chip processor, one after another, in preparation for transmission within a ring network. (17) The step b) includes the step of setting a transmission flag indicating that one of the one-chip processors is "ready to transmit." method. (18) The above-determined transmission right granting procedure is based on CSMA.
/CD procedure according to claim (16). (19) In the post-send pause, all one-chip processors that are ready to transmit, if the ring transmission path is statistically allowed and time-varying, After accessing a processor transmission collision, it is checked whether the ring transmission path is free, and this check is repeated until data transmission is completed for all the one-chip processors by the one-chip processors that have been given the transmission right. The system according to claim 16, wherein the one-chip processor holds the transmission right during the transmission. (20) The data sent by one of the one-chip processors is subdivided into blocks, each of which is checked by the receiving one-chip processor and returns an error signal to the sending one-chip processor if there is an error. 17. The method according to claim 16, wherein among the received data, the transmitting one-chip processor retransmits only blocks containing errors before including them in the transmission. (21) The one-chip processor receives data transmitted via the ring transmission path and passes through the ring transmission path,
Claim No. 16, wherein data received by the one-chip processor is compared and checked.
Method described in section. (22) The first one-chip processor that is requested to respond to the reception of the data sent by the second one-chip processor, the first one-chip processor to which the response is sent, sends the response. 19. The method according to claim 18, wherein the transmission right is taken over from the second one-chip processor at a later date, and the transmission right is returned to the second one-chip processor after the transmission is completed. (23) After transmission is completed, if no other one-chip processor is ready to transmit, that one-chip processor retains the transmission right and periodically repeats providing the transmission right to other one-chip processors. Claim No. (
16) Method described in section 16). (24) After the transmission is completed, if the other one-chip processor is not ready for transmission or has stopped its transmission operation, the one-chip processor retains the transmission right. The method described in (18). (25) When a one-chip processor receives data from the one-chip processor that is transmitting it, prior to the data, the receiver address, the source address of the one-chip processor that is transmitting, the destination address to which the data is sent, and the data Claim No. 16, in which a header containing a fetching address from which a message is fetched, a block of transmitted numerical data, a check sum of data including the header, etc. is first transmitted.
).