JPS6184940A - Token passing network system - Google Patents

Abstract

PURPOSE:To relinquish a packet arriving within a loop circulating time from the loop as an own station transmission packet by providing a counter started just after the start of packet transmission to each station and counting a transmission clock. CONSTITUTION:An asynchronous area DASY data is delayed for a time required for transmission/reception and relinquishment by a delay circuit 28, fed to an SD detector 29, an ED detector 30, a packet transmission circuit and a control section 31, where a header SD, an end ED and a tomen TK of a packet signal are detected respectively. An output of the circuits 29, 30 is fed to a relinquishing gate control circuit 33 and an output of the control section 31 is fed to the circuit 33 via a counter 32. Then the circuit 33 uses a signal from the counter 32 and the detector 29 to discriminate the own station transmission packet, and uses a signal of the detector 30 to output a lost signal of the SD and ED of the own station transmission packet and the relinquishment gate 34 relinquishes the own station transmission packet passing through the circuit 28.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a token passing network 7 system using a loop network with a mixture of synchronous and asynchronous data used for local communication.

Configuration of the conventional example and its problems A conventional example of the 7-stem loop transmission system to which the present invention is applied is described in the first example.
As shown in the figure. This transmission 7 stem has the function of circulating a fixed length frame on a loop at a constant period, and the center station (C8) 1 that manages the disappearance of tokens in the asynchronous data area (packet exchange area) in the frame, and the synchronization Remote stations (R3) 2, 3.4, which transmit and receive data in the data area (circuit switched area) and packets in the asynchronous data area, are connected by a line 5. .7.8.
9 and packet switching terminals 10°11.12.13 are connected.

FIG. 2 shows the frame structure on the loop transmission path.

This frame includes a frame header part (FH) consisting of a frame synchronization signal (FS) and additional information ("MPX").
, a fixed-length frame consisting of a synchronous data area (DSYN) in which circuit-switched data of a circuit-switched terminal exists and an asynchronous data area (DASY) due to token passing of a packet-switched terminal.

Because there is not just one frame shown in Figure 2 on the transmission path due to the delay of the signal on the transmission medium and the delay at each station, the CS has an internal phase adjustment circuit using elastic memory, and the loop −Adjust the cyclic delay time to an integral multiple of the frame period, and on the loop,
A positive integer number of frames exist.

Figure 3 is a functional block diagram of each station.
4 is a loop transmission path, 15 is a frame synchronization established, and FH
The data section following is divided into synchronous data (DSYN) and asynchronous data (DAsY), and each is divided into circuit switched adapter (PBX) 1e and packet switched adapter (PAD).
17 is a time division multiplexing/demultiplexing circuit (TDMA) for distributing the signals. Reference numeral 16 denotes a PBx 16 that separates and inserts data from the circuit switching terminal 18 connected to its own station from the synchronization data from TDMAls. 17 packetizes the data of the packet switching terminal 19 into the asynchronous data from the TDMA 15, and
) and transmits the number node, and the function of receiving packets from the station/station-connected packet switching terminal 19 in asynchronous data. This P.A.D.
The token passing performed in 17 is a token passing method (hereinafter referred to as multi-frame token pano/nkto) that releases the TK immediately after sending a packet.

Note that the DATDMA (dynamic assignment time division multiplexing/demultiplexing circuit) of the CS has an elastic memory for adjusting the number of frames existing on the loop to an integer number.

FIG. 4 shows the packet exchange performed in the DAsY area. In the figure, SD is the packet header, DA is the destination address, SA is the source address, and IN
FO is transmission data from the packet switching terminal 19, Fe2 is a frame check sequence, and ED is a packet chain. TK is a token, and in a method in which the token is released immediately after sending a transmission packet, TK continues immediately after ED.

FIG. 5 shows packets on an actual synchronous/asynchronous data mixed loop. There are a number of frames determined by the system on the loop, but for the sake of explanation, Fl, F2 in the figure
Assume that there are frames. The beginning of Fl and the end of F2 are continuous.

In the figure, the shaded areas represent sections other than the asynchronous data area.

The packet is stored in the asynchronous data area (D
Pl
is such an example. F2 is another packet. In multi-frame tor7 bashing, it is possible to concatenate packets, and immediately after the last packet on the loop, T
K exists.

In conventional token passing, the transmitting station deletes the transmitted packet from the loop by comparing the source address (SA) of the packet arriving after transmitting the packet with its own station address (MA).

FIG. 6 shows a conventional sending packet sending circuit in a PAD. In the figure, 20 is a delay circuit that delays the DAsY data from TDMA by the necessary transmission/reception and erasing processing time within the PAD and forms a bypass path;
is a header SD detector for detecting SD from DASY, 22 is an MA register that stores its own station address (MA), and 23 is a SD detection signal from 21 to compare SA and MA in the packet. SA comparator,
24 is an ED detector that detects ED from DsAY; 25
26 is activated by the packet transmission start signal from 25, and when a packet transmitted from the own station arrives from the upstream of the loop, the erase gate is activated. This is a sending packet erasure controller that controls and erases this from the loop, and the SD detector 2
1 and the output of the SA comparator 23, the SA detects a packet that matches its own station, and from the signal from the ED detector 24, SA to E of the packet sent out from the own station is detected.
It has a function of outputting a gate signal for erasing Dt to the gate circuit 27. Reference numeral 27 denotes an erasing gate for erasing the self-station sending packet in the bypass data passing through the delay circuit 20 in accordance with the output of the sending packet erasing controller.

In such a PAD, in order to reduce the data delay per station, the internal delay PDLY has at most several bytes. However, 1) the SYN area is
PLILY distance is also set much larger.

Therefore, the packet spans two DAsY areas,
In a special case where the positional relationship is as shown in FIG. 7, the SD of the own ST transmission packet may not be erased.

FIG. 7 is a diagram showing the positional relationship between the packet and areas other than L)AsY. In the figure, the shaded area indicates areas other than DAsY. A is a case where SD and DA and subsequent parts are separated by a shaded area, and B is a case where SV and vA and SA and subsequent parts are separated.

In either case, since the PDLY in the PAD 17 is smaller than the length of the shaded area, the SLI has already passed through the PAD and then the TDMA 15 by the time SA determines that the packet is a packet to be sent from the own station.

It will be output on the loop.

For this reason, when erasing packets sent from the own station after determining SA, there are cases where Ei) can be erased but SD cannot be erased.

In this way, when SD remains on the loop, after a certain station sends out a packet, the remaining SL+ arrives before the sent packet returns, and it is determined that the sending bucket and door have disappeared, resulting in a transmission failure. There was a problem.

As a solution to this problem, there is a method of determining that a packet that arrives at a sending station after sending a packet is a packet sent by the station itself, and erasing this packet. This is a method of determining the sending packet based only on the SL), but in multi-frame token passing, the packets circulate in a connected manner, so if the first packet is lost, all transmitting stations will There was a problem in that the data was erased one batch at a time, and errors were propagated.

Purpose of the Invention The present invention solves the above-mentioned problems, and is intended to solve the above-mentioned problems.
To realize a token passing method that eliminates omissions in packet erasure and ensures reliable packet erasure.

Configuring the Invention According to the present invention, each station has a counter that starts immediately after the start of packet transmission, and counts the transmission line clock, and the packets that arrive at the roof sequential time are treated as self-station transmission packets from the loop. This is a pan-sync network system that combines synchronous and asynchronous data and is characterized by data erasure.

DESCRIPTION OF THE EMBODIMENTS An embodiment according to the present invention is shown in FIG. Figure 8 shows the PAJ
This is a sending packet erasing circuit in J.

In the figure, 28 is the DASY data from TDMA, PAD
29 is a delay circuit that delays the necessary transmission/reception and erasure processing time within the DASY and serves as a bypass path; 29 is an SD detector that detects an SD from within DASY;
30 is an ED detector that detects (outputs) ED from DASY; 31 is a packet sending circuit and its controller unit that detects TK from DASY and sends out a packet; 32 is a controller for starting packet sending from 31; A counter that is activated by a signal and accurately measures time by counting the transmission line clock;
33 is a sending packet eraser which determines the packet sent out from the own station from the signals from the counter 32 and the SD detector 29, and outputs an erase signal from SD to ED of the packet sent from the own station based on the signal from the ED detector 30. The controller 34 is an erase gate that erases the own station sending packet passing through the delay circuit 28 based on the output of the sending packet erase controller 33.

According to the present invention, information on the Lugou travel time on the transmission path;
In order to judge the sending packet based on the SD pattern,
5. There is no need to judge A. It becomes possible to immediately erase the SD, and no SD remains.

In addition, since the sending packet is determined not only by the arriving SD but also by the Lugou round trip time, even if the first packet of the sending packets connected on the loop is lost, the sending packets from other stations will not be erased by mistake. , errors are not propagated to packets sent to other stations.

Since the loop-delay time is measured by counting the transmission line cross-returns, the loop-delay time can be stably measured even if the loop-delay time changes slightly due to temperature changes or the like.

The transmission line clock is much more reliable information than the transmission line data, so depending on the data pattern such as SA,
A more stable erasing operation can be performed than erasing packets.

Note that even if the counter value is not set exactly to the Rougou round trip time, by allowing a margin of ±α (α: minimum packet length), the feasibility of hardware and the stability of operation are improved.

Furthermore, even when the allocation of the synchronous data area and the asynchronous data area changes dynamically, the present invention ensures that no header SD is left unerased, and a reliable erasing operation can be performed.

Effects of the Invention According to the present invention, when token hashing is performed in a synchronous/asynchronous data mixed loop, it is possible to reliably erase transmitted packets, and furthermore, a stable erasing circuit can be realized.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a loop transmission system to which the present invention is applied, Fig. 2 is a frame block diagram, Fig. 3 is a block diagram of a spoon 1, Fig. 4 is a packet block diagram, and Fig. 5 is a block diagram of a loop transmission system to which the present invention is applied. The diagram is
A diagram showing the configuration of packets on a transmission path. FIG. 6 is a diagram showing the configuration of a conventional packet erasing circuit. FIG. 7 is a diagram showing the packet configuration for explaining the conventional example. FIG. 8 shows the configuration of the packet erasing circuit according to the present invention. It is a diagram. 1... Center station (C3), 2-4...
...Remote station (R3), s...
・Loop transmission line, 6 to 9...Line switching terminal, 1
0 to 13... Packet switching terminal, 14... Loop transmission line, 16... Time division multiplexing/demultiplexing circuit (TDMA
), 16... Line exchange adapter (PBX), 17
...Packet exchange adapter (PAD), 18...
.... circuit switching terminal, 19... packet switching terminal, 2o... delay circuit, 21...-3D detector, 22... MA register, 23...・・・・・・
Comparator to S, 24...-ED detector, 25...
Packet sending circuit and controller, 2... Sending packet erase controller, 27... Erasing gate, 28... Delay circuit, 29... SD
(Header) Detector, 3o...-ED detector, 31.
...Packet sending circuit and controller, 32.
. . . Counter, 33 . . . Output packet erasure controller, 34 . Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 7fθ Figure 2 Figure 3 Figure 4 Figure 6

Claims (1)

[Claims] Stations that send and receive data are connected by a loop transmission path, and each station has a circuit switching terminal that sends and receives data that is synchronized with the loop transmission path clock, and a packet switching terminal that sends and receives data that is asynchronous to the loop transmission path clock. The circuit switching terminal performs circuit switching using the synchronous data area in an integer number of frames circulating on the loop transmission path at a constant cycle, and the packet switching terminal performs circuit switching using the synchronous data area in the frame. is used to exchange packets by token passing. In token passing, the packet sending station releases the token immediately after sending the packet, and each station has a counter that operates when the packet is sent and counts the clock of the transmission line. By doing so,
A token passing network system is characterized in that immediately after the start of packet transmission, packets that return after one cycle of the loop are deleted as self-station transmission packets.