JPS6184929A - Synchronizing controller - Google Patents

Abstract

PURPOSE:To detect a transmission timing error of a reference station synchronizing burst with sufficiently high accuracy by providing a timing error detection circuit having a measuring pattern storage circuit and a parallel/serial converting circuit. CONSTITUTION:When a measuring gate is inputted to a timing error detection circuit 13, a leading detection circuit 17 detects the leading to start count (18). Its output signal is selected by a selection circuit 19, is fed to a measuring pattern storage circuit 16 and stored in a designated address sequentially in the unit of 8-bit. When a full measuring code is stored in the circuit 16, the leading of the measuring gate is detected (20), and the content of the circuit 18 is cleared. Then the count of a counter circuit 22 for write timing of a parallel/serial converting circuit 24 and a counter circuit 21 for read address of the circuit 16 is started at the same time and the circuit 19 controls the circuit 21 so that an output of the circuit 21 is selected. Thus, the transmission timing error of the reference station synchronous burst is detected with sufficiently high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous control device for a satellite switch time division multiple access communication system. The present invention relates to a synchronization control device for a time division multiple access communication frame generated by a matrix switch circuit of a communication satellite by a reference station that provides a time reference for a general earth station in a satellite switch time division multiple access communication system.

[Conventional technology]

Satellite switch time division multiple access a (SS, TDMA)
The communication method is one of the important methods for future large-capacity satellite communication, and the matrix switch circuit (MSM) of the reference station in the satellite switch time division multiple access communication method.
The synchronization control to the time division multiple access frame created by the time division multiple access frame is an important basic technology in this system. Furthermore, the most important matter in the above synchronization control is how accurately the time reference of the time division multiple access frame created by the matrix switch circuit is detected. In order to detect the time reference of a time division multiple access frame created by a conventional matrix switch circuit, a measurement code (METtC code) is created by adding the trailing edge of a special reference station synchronization window to the rear of the reference station synchronization burst for the reference station to perform synchronization control. ) is known to be detected in an analog or digital manner.

Prior application: Japanese Patent Application No. 59-73810 [Problems to be Solved by the Invention] However, the detection accuracy of the conventional methods was insufficient, and improving the detection accuracy resulted in a significant increase in the amount of hardware.

SUMMARY OF THE INVENTION The present invention aims to overcome the above-mentioned drawbacks and aims to provide a synchronization control device which provides the necessary and sufficient accuracy of detecting the time reference of a time division multiple access frame with a relatively simple circuit.

[Means for solving problems]

The present invention provides demodulation means for demodulating a measurement code added to the rear of a reference station synchronization burst that is cut off by the trailing edge of a reference station synchronization window created by a matrix switch on a communication satellite, and the timing of the measurement code from this demodulation means. In a synchronization control device for a satellite switch time division multiple access communication system, the synchronization control device includes a means for detecting an error with a reference value, and a transmission timing control means for controlling the transmission timing according to the output of the means. , a measurement pattern storage means for storing the one-symbol parallel measurement code from the demodulation means from the start point to the end point; and a measurement pattern storage means that reads out the measurement code in units of several symbols from the measurement pattern storage means and converts it into a serial signal. It is characterized by comprising a parallel-to-serial conversion means for outputting.

[For production]

The present invention stores the measurement code in a storage means in a low-speed section where the measurement code is processed in parallel, converts a parallel signal in units of several symbols into a serial signal from the storage means, and converts this serial signal into a parallel signal. By detecting the correlation in units of several biyl, outputting a detection signal when the value exceeds the threshold value, and measuring the time from the start point of the measurement code until the detection signal is generated, the reference station can be accurately detected. Detection of the trailing edge of the synchronization window can be performed.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

The second part is a schematic diagram of a satellite switch time division multiple access communication system to which the synchronous control device of the present invention is applied. Second
In the figure, ■ is the satellite-mounted receiver, 2 is the matrix switch circuit, 3 is the satellite-mounted transmitter, 4 is the multi-beam antenna, 5 is the earth station, and A, B, C, and D are the spot beam zones. - each earth station 51-5. in four spot beam zones A, B, C, D by way of example;
The matrix switch circuit 2 performs predetermined time division multiple access communication. Spot beam zone A,
Earth stations 51 to 5 in B, C, and D. are each connected to a receiver 1 on the satellite via a multi-beam antenna 4. The output of the receiver 1 is connected to a matrix switch circuit 2, and after predetermined switching is performed, it is connected to a transmitter 3.

FIG. 3 is a diagram showing an example of a connection mode of the matrix switch circuit 2 that switches and connects each spot beam zone A to D in the time division multiple access communication system shown in FIG. 2. In FIG. 3, the first time slot of the time division multiple access frame is such that the signal transmitted from spot beam zone B is received by all spot beam zones A-D, and the last time slot of the time division multiple access frame is such that the signal transmitted from spot beam zone B is received by the spot beam zone B. From zone C to spot beam zone 8, from spot beam zone D to spot beam zone B,
Spot beam zone A with spot beam zone C
This shows that the beam is transmitted from spot beam zone B to spot beam zone D. Note that in this example, the reference station is located in spot beam zone B.

FIG. 4 shows the local station return window (the time slot in which the signal passes through the matrix switch circuit 2 is called a window) when the satellite is viewed from spot beam zone B in the connection mode shown in FIG. A reference station synchronization window 102 is a slave station synchronization window and a data window.

FIG. 1 is a block diagram of a satellite switch time division multiple access communication system including a synchronization control device in a reference station. In FIG. 1, synchronous burst generation circuits 6 to 5
The reference station synchronous perspective 04 shown in the figure is connected to the modulation circuit 7, and the modulation circuit 7 outputs P S K (Phase 5hi
ft Keying) The modulated signal is transmitted to the communication satellite 9 via the transmission circuit 8.

In the communication technique X9, it is connected via the receiver l with the matrix switch circuit 2,
The signal is then switched and connected and transmitted from the transmitter 3 to the earth station 5. The earth station 5 is connected to a demodulation circuit 12 in a synchronous control device 11 via a reception circuit IO.

Here, the feature of the present invention is the timing error detection portion surrounded by a dashed line. That is, the demodulation circuit 12
The reference station synchronization burst demodulated from the reference station is connected to the timing error detection circuit 13. Timing error detection circuit 13
The transmission timing error detected from the transmission timing error is connected to the transmission timing control circuit 14.

A control signal from the transmission timing control circuit 14 is connected to the synchronous burst generation circuit 6.

The operation of the synchronous control device having such a configuration will be explained. The reference station synchronous burst 104 shown in FIG. 5 generated by the synchronous burst generation circuit 6 is subjected to PSK modulation to the intermediate frequency signal carrier wave by the modulation circuit 7, and is transmitted to the communication satellite 9 via the transmission circuit 8. . In the communication satellite 9, the signal is transmitted via the receiver 1, the matrix switch circuit 2, and the transmitter 3 to the earth station 5. At earth station 5, receiving circuit 1
The reference station synchronization burst 104 enters the demodulation circuit 12 via 0, and the reference station synchronization burst 104 demodulated here is sent to the timing error detection circuit 13.
A transmission timing error is detected, and based on the result, the synchronous burst transmission timing control circuit 14 correctly controls the transmission timing of the reference station synchronous burst.

FIG. 5 is a diagram showing the normal positional relationship of the reference station direction and period bursts in the reference station synchronization window, and the timing is controlled so that the reference station synchronization burst 104 has the relationship as shown in FIG. 5 in the reference station synchronization window 101. . That is, the reception timing 106 of the burst identification code (Unique code) in the reference station synchronization burst 104
The time difference between this and the timing 107 at which the measurement code attached to the rear of the reference station synchronization window 101 is cut off at the trailing edge 103 of the reference station synchronization window 101 is constantly controlled to be a predetermined value.

As described above, the reference station in the satellite switch time division multiple access communication system synchronizes with the time division multiple access frame created by the matrix switch circuit 2 of the communication satellite 9 using the reference station synchronization hearth 04, and other slave stations are transmitted by the reference station. A synchronization burst is received from a reference station that is synchronously controlled to serve as a time reference for a time division multiple access frame.

The feature of the present invention is that the reference station uses the measurement code of the reference station synchronization burst 104 to control the trailing edge of the reference station synchronization window 101 at a low speed (1/8 to 1/1 of the symbol rate).
In step 6), detection is performed with high-speed bit-by-bit precision for each time division multiple access frame, and the detection is performed with high precision using a relatively simple circuit. The contents will be explained in detail with reference to FIG.

FIG. 6 is a block diagram of the timing error detection circuit of the synchronous control device according to the embodiment of the present invention. In FIG. 6, for example, the measurement codes of channels P and Q (in the case of 4-phase PSK modulation method 2) that are low-speed converted into 8-bit parallel signals are logic "0" if they are received normally. It is assumed that the timing error detection circuit 13 is interfaced. 8hi.

The measurement code of the 8-bit parallel channel P is input to the input terminals 511 to 51fi of the timing error detection circuit 13, and the measurement code of the 8-bit parallel channel Q is input to the input terminal 52. 〜52□ is input.

The measurement codes of channel P and channel Q input to the timing error detection circuit 13 are OR gates 15, ~15.
, a match is detected bit by bit from the beginning of the measurement code. If both channel P and channel Q are received normally, then 5. ~15. The output will be logic "0", indicating that one or both of channel P and channel Q are being received in error.15. ~
The output of 15fi becomes logic [lJ.

15. Calculate the measurement codes for channel P and channel Q using the keyboard. The purpose of detecting coincidence by 157 is to use the randomness of the received code to make the trailing edge of the base station synchronization window clear after the measurement code is cut off by the trailing edge of the base station synchronization window. Therefore, two-phase P
In the case of the SK modulation method, the measurement code corresponding to the channel Q is not input.

The 8-bit measurement code detected as a match is temporarily stored in the measurement pattern storage circuit 16. In this way, all the measurement codes are stored in the measurement pattern storage circuit 16 after the channel P and channel Q are detected to match each other in 8-bit order.

That is, the code stored in the measurement pattern storage circuit 16 is a code in which one or both of the measurement codes of channel P and channel Q were received in error. On the other hand, timing control of writing to or reading from the measurement pattern storage circuit 16 is performed by a measurement pattern 105 shown in FIG. 5 that is input to the input terminal 53. This measurement gate width is equal to the length of the measurement code.

In the timing error detection circuit 13, the measurement gate 1
When 05 is input, the rising edge is detected by the rising edge detection circuit 17, and counting by the writing address counting circuit 18 of the measurement pattern storage circuit 16 is started. The output signal of the counting circuit 18 is selected by the selection circuit 19 and supplied to the measurement pattern storage circuit 16, whereby the measurement code is sequentially stored in the designated address in units of 8 bits as described above.

When all the measurement codes are stored in the measurement pattern storage circuit 16, the measurement gate 105 falls, and the falling detection circuit 2
0, the falling edge is detected and the contents of the counting circuit I8 are cleared, and the reading address counting circuit 21 and the parallel-to-serial converting circuit 2 of the measurement pattern storage circuit 16 are cleared.
Counting by the counting circuit 22 for the write timing of 4 is started, and the selection circuit 19 is controlled to select the output of the counting circuit 2.

In this way, all measurement codes are stored in the measurement pattern storage circuit 16.
8 from the beginning of the measurement code as soon as the memorization is completed.
Reading is started in units of hints.

The measurement code read out from the measurement pattern storage circuit 16 in units of 8 bits is converted into an appropriate value by the counting circuit 22 and sent to the decoder 2.
The data is written to the parallel-to-serial conversion circuit 24 according to the timing extracted by No. 3. On the other hand, measurement pattern memory circuit 1
Counting by the timing error counting circuit 31 is started only at the timing when the first 8-bit measurement code read from 6 is written into the parallel-to-serial conversion circuit 24. Here, the counting circuit 22 is an 8-bit counting circuit, and the counting circuit 21 is an 8-bit counting circuit.
are configured to operate synchronously at 1/8 the speed of the counting circuit 22. However, this is an operation when the measurement code is processed in 8-bit units, and does not apply when it is processed in 4-bit units or 16 and 7) units.

The measurement code written in the parallel-to-serial conversion circuit 24 is converted into a serial signal and is supplied bit by bit to the serial-to-parallel conversion circuit 25 at the next stage. The measurement code is shifted one bit at a time by the serial/parallel conversion circuit 25, and the number of error bits within a range of, for example, 8 bits is output for each symbol. Here, the range of bits within which the number of error bits is to be viewed can be arbitrarily set depending on how many pinpoints of the number of output bits of the serial/parallel conversion circuit 25 are to be viewed simultaneously.

The output of the serial-to-parallel conversion circuit 25 enters the correlation detection circuit 26, where when the number of erroneous binots within 8 pintos becomes larger than the value set by the threshold setting circuit 27, the output signal is sent to the next stage. It is supplied to the serial/parallel conversion circuit 28. Similarly, the number of error bits within the appropriately set bit number range is compared in the correlation detection circuit 29 with the value set by the threshold setting circuit 30, and if the number is larger than the set threshold, When this happens, a signal is output, and the timing error counting circuit 31 stops counting when the signal rises. The count value of the counting circuit 31 at this time is expressed by the number of symbols from timing 106 to timing 107 shown in FIG. Therefore, this value is the output terminal 541
~54. ．． and is supplied to the next stage synchronous burst transmission timing control circuit 14. Here, it is compared with a specified value, and the number of symbols corresponding to the error is used as transmission control information.

Here, the timing error detection circuit 13 performs two-stage detection on the number of error codes in the received measurement code, but it is possible to detect timing errors even with one-stage correlation detection. . However, in the present invention, two-stage correlation detection is performed for the purpose of increasing detection accuracy, and a second-stage correlation detection circuit is provided for the purpose of compressing the data obtained by the first-stage correlation detection. .

By doing so, as described above, it is possible to detect the transmission timing error of the reference station synchronization burst with sufficient accuracy for practical use using a relatively simple circuit. If it is desired to further improve the detection accuracy, the objective can be achieved by averaging or integrating the detected values over several time division multiple access frames to several tens of time division multiple access frames.

〔Effect of the invention〕

As explained above, the present invention is a method for a reference station to perform synchronization control on time division multiple access frames created by a satellite matrix switch circuit, which is the most important technology in the satellite switch time division multiple access communication system. This has an excellent effect in that the trailing edge of the reference station synchronization window, which serves as a time reference, can be detected with a predetermined accuracy using a relatively simple circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a satellite switch time division multiple access communication system to which the synchronous control device of the present invention is applied. FIG. 2 is a schematic diagram of a satellite switch time division multiple access communication system to which the synchronous control device of the present invention is applied. FIG. 3 is a diagram showing connection modes using the satellite matrix switch circuit. FIG. 4 is a diagram showing the local station return window as seen from the B beam zone in FIG. 2. FIG. 5 is a diagram showing a state in which a reference station synchronization burst is transmitted at a normal timing in a reference station synchronization window. FIG. 6 is a block diagram of a timing error detection circuit of a synchronous control device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Onboard receiver, 2... Matrix switch circuit, 3... Onboard transmitter, 4... Multi-beam antenna, 5... Earth station, 6... Synchronous burst generation circuit,
7... Modulation circuit, 8... Transmission circuit, 9... Communication satellite, 10... Receiving circuit, 11... Synchronization control device, 1
2... Demodulation circuit, 13... Timing error detection circuit, 14... Transmission timing control circuit, 15... OR gate, 16... Measurement pattern storage circuit, 17...
・Rise detection circuit, 18.21.22... counting circuit,
19... Selection circuit, 20... Fall detection circuit, 23
. . . decoder, 24 . . . parallel-serial conversion circuit, 25.
28...Serial parallel conversion circuit, 26.29...Correlation detection circuit, 27.30...Threshold setting circuit, 31...
- Timing error counting circuit, 51.52.53... Input terminal, 54... Output terminal, 101... Reference station synchronization window, 103... Trailing edge of reference station synchronization window, 104... Reference station synchronization burst , 105...Measurement gate, 106...Reception timing, 107...
The timing at which the measurement code is determined at the trailing edge of the reference station synchronization window.

Claims (1)

[Claims] (1) demodulation means for demodulating the measurement code added to the rear of the reference station synchronization burst cut off by the trailing edge of the reference station synchronization window created by the matrix switch on the communication satellite; In a synchronous control device for a satellite switch time division multiple access communication system, which includes means for detecting an error with a reference value, and a transmission timing control means for controlling transmission timing based on the output of this means, the means for detecting the above-mentioned A measurement pattern storage means for storing the measurement code of one symbol parallel from the demodulation means from the start point to the end point; and a measurement pattern storage means for reading out the measurement code in units of several symbols from the measurement pattern storage means and converting it into a serial signal. 1. A synchronous control device comprising: parallel-to-serial conversion means for outputting a signal.