JPS6182528A - Level detecting circuit of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To execute an operation which receives no input signal for a prescribed time after detecting an input signal, also to make a clock pulse unnecessary, and to reduce current consumption by constituting a circuit of a ratioless circuit, a delay holding circuit and a delaying circuit. CONSTITUTION:An input node is formed by connecting each gate of T2 and T3 of a ratioless circuit formed by connecting in series P channel MOS transistors T1, T2 and N channel MOS transistors T3, T4, an inverter circuit 3 and a delaying circuit 10 are connected successively to the post-state of the drain each connecting point of T2 and T3, a series circuit of T1-T4 is formed as a ratioless circuit 11 by connecting this output node N'2 to each gate of T1 and T4, and a series circuit of transistors T5-T8 is formed as the second ratioless circuit 12. A delay holding circuit 13 is formed by the inverter circuit 3 and the second ratioless circuit 12, and after an input signal has been held by the delay holding circuit 13, no input signal is received for a prescribed time until a delay signal is outputted from the delaying circuit 10.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a level detection circuit that can be used in an input buffer inverter circuit, etc. of a semiconductor integrated circuit, and particularly relates to a level detection circuit using complementary MOS transistors. Regarding circuits.

[Technical background of the invention]

2. Description of the Related Art A level detection circuit having a function of not accepting an input signal for a certain period of time after detecting an input signal is sometimes used as an input buffer or the like of a semiconductor integrated circuit. A conventional example of this type of level detection circuit is shown in FIG. 5), which converts, for example, a TTL level input into a MOS level. That is, in FIG. 5, 1 is a first clocked inverter, which connects P-channel MO8 transistors T□, T2 and N-channel MOS transistors T3, T
4 are connected in series, the source of the transistor T□ is connected to the high potential side power supply vDD, and the transistor T
The source of the transistor T4 is connected to the power supply vss on the low potential (ground potential) side, a clock pulse φ is applied to the gate of the transistor T4, an inverted clock pulse φ is applied to the r-) of the transistor Tff, and the transistor Tffi #TI
The gates of are connected to each other to form an input node N8. Similarly, the second clocked inverter 2 is a P-channel transistor.

T3, T3, N-channel transistor T7.

From T, an inverted clock pulse φ is applied to the r-to of the transistor T1, and an inverted clock pulse φ is applied to the r-to of the transistor T1, and the gates of the transistors T@sTt' are connected to each other to the output node N2. It is connected. a transistor T3 of the first clocked inverter 1;
The drain interconnection point (node NS) of T, is connected to the input end of the inverter circuit 3 and the transistor T of the second clocked inverter 2.

connected to the drain interconnection point (node N4) of T,
The output end of the inverter circuit 3 is connected to the output node N2. With the above connection, the inverter circuit'NI
3 and the second clocked inverter 2 form a delay hold circuit 4.

FIG. 6 is a timing diagram showing operating waveforms of the circuit shown in FIG. 5. That is, before time t1, clock pulses φ and φ are respectively low (“L”) and high (“H”).
Once the node N of the first clocked inverter 1 is in the floating state, the second clocked inverter 2 is in the access state and the output is
, are held at high level, and node N4 is held at low level. Note that the input signal of the input node N□ at this time is, for example, a low level.

Next, at time point 11, when the clock pulses φ and φ change to high and low levels respectively, the first side clocked inverter 1 changes from the loading state to the access state, and the second clocked inverter 2 changes from access state to floating state. As a result, the node N□ is inverted from low level to high level at time t2, and the output node N2 is inverted from high level to low level at time 11. Here, the time difference between t and t,
1. ．． 1. The time difference is the delay associated with circuit operation. Next, at time point 14, when the clock pulses φ and φ respectively change to low and high levels, the clocked inverter 1 of ml changes from the access state to the 70-ting state again), and the second clocked inverter 1 changes from the access state to the 70-ting state. Inverter 2 changes from floating state to access state, sets node N4 to high level,
The output node N is held at a low level. Above 1
From time point 4 to time point t6, the levels of clock pulses φ and φ do not change, and in this state, even if the input signal changes, it is not detected.

That is, even if the input signal changes from low level to high level at time point 11, the input signal is not transmitted because the first clocked inverter 1 is in a floating state. Next, at time t6, when the clock/4 pulses φ and φ change to high and low levels respectively, the first clocked inverter l enters the access state and transmits the input signal to the next stage, and the second clock The inverter 2 becomes in a floating state. At time t7, node N becomes low level, which is the inverted input signal from the previous stage.The low level of node N is inverted by inverter circuit 4, and output node N2 becomes high level at time ts. At time t9, when the clock pulses φ and {circle around (2)} respectively change to low and high levels, the first clocked inverter 1 is no longer in a floating state, and the second clocked inverter 2 is in an access state. , As a result, the second clocked inverter 2 maintains the output node N at a high level, and the first clocked inverter 1
does not accept input signals.

[Problems with background technology]

However, since the conventional level detection circuit described above requires two types of clock pulses φ and ■ of positive phase and negative phase for operation control, it is necessary to supply them from within the integrated circuit or to create them within the integrated circuit. There is a drawback that. Furthermore, since the level detection circuit is a ratio circuit, a through current flows especially when a TTL level is input (for example, at node N).

flows into the first clocked inverter 1 when the signal changes from high level to low level) and output node N2.
It also has the disadvantage of deteriorating the waveform.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is capable of operating in such a way that it does not accept input signals for a certain period of time after detecting an input signal, does not require clock pulses, and reduces current consumption. The present invention provides a level detection circuit that can be

[Summary of the invention]

That is, the level detection circuit of the present invention includes a ratioless circuit transistor T, which includes a P-channel MOS transistor T'xtT'* and an N-channel MOS transistor T3, T, which are connected in series.

The gates of T3 are connected together to form an input node, and a delay holding circuit and a delay circuit are sequentially connected after the drain interconnection point of the transistor T'*tT'm, and the output terminal (output node) of this delay circuit is The potential of the transistor T
It is characterized in that it is applied to the gates of 1 and T.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The level detection circuit shown in FIG. 1 has a delay circuit 10 connected in series between the output terminal N2 of the inverter circuit 3 and the output node N'2, compared to the conventional circuit described above with reference to FIG. and connect this output node N/ with a transistor.
The input node N8 is connected to each gate of T4, and the input node N8 is a transistor T,.

By connecting to each gate of T, the series circuit of transistors T and T is made into a first ratioless circuit 1, and the series circuit of transistors T and T is made into a second ratioless circuit 12. The stones are designated by the same symbols as in Figure 5 because they are the same except for the stones in Figure 5. Note that a delay holding circuit 13 is formed by the inverter circuit 3 and the second ratioless circuit 12.

FIG. 2 is a timing diagram showing operating waveforms of the circuit shown in FIG. 1. That is, before time t1, the input node N
For example, if the input signal of the device is at a low level, the node N is at a high level, the node N is at a low level, and the output signal of the output node N' is at a high level.

When the input signal changes to high level at time t, transistors 'r3, 'r are turned off, and transistors T3, T,
is turned on. At this time, the transistor T4 is turned on by the high level of the output node N/, so
Node N changes from high level to low level. Also, at this time, the transistor is turned off by the high level of the output node N'8, so there is no through current in the first ratioless circuit 11, and the potential change at the node N becomes sudden and steep. . At the time t1 when the potential of the node N changes, which is delayed by the operation delay time, the output terminal (NO) of the inverter circuit 3 changes from a low level to a high level. As a result, transistor 6 is turned off and transistor T7 is turned on. At this time,
Since the transistor T8 is turned on by the high level of the input node N, the delay holding circuit 13 is turned on by the high level of the input node N.
4 is held at a low level and note N is held at a high level. On the other hand, the output signal of the delay circuit 10 is at the node N
2, the potential change time t is delayed by the operation delay time ts
At this point, the signal changes from high level to low level. Note that even if the input signal changes from high level to low level at time t4 between time ts and time t,
At time 4, the delay circuit 10 outputs the node N at time ts,
Since the level of T has not yet been transmitted to the output node N/, the transistor T of the first ratioless circuit 11 is turned off, the transistor T4 is turned on, and the input signal is not transmitted. Further, at the time point t4, the second ratioless circuit 12 has a transistor Ts.

Since T7 is on and transistors 'r3 and 'r are off, the state is 70-ting, but the node N
! level is maintained dynamically. Then, due to the change in the potential of the output node N' at the time t, the first ratioless circuit 11 turns on the transistor T1 and turns off the transistor T4, so that the input signal is transmitted to the next stage.

The level detection circuit shown in Figure 1 above can be used in any circuit part in an integrated circuit to detect a MOS level input signal and
9. It is possible to obtain a level output signal by optimizing the threshold of the MOS transistor in the first ratioless circuit 11. It is suitable as an input buffer circuit for converting TTL level input to MOS level. For example, the threshold f of transistor T, 3.5V
.

When the threshold of transistor T is set to 1.5V, as shown in Figure 3, the threshold of transistors T3 and T is between the TTL input voltage levels, so even if there is a little noise on the input level, the next It is difficult for signals to be transmitted between stages.

According to the level detection circuit as described above, since a clock pulse is not required and a ratioless circuit is used, no through current flows, and low power consumption and high-speed operation can be achieved. In addition, the input signal is not accepted for a certain period of time after the input signal is held in the delay holding circuit 13 until the delayed signal is output from the delay circuit 10.

FIG. 4 shows another embodiment of the inventive circuit), which is inserted between the output and input of the inverter circuit 3, compared to the circuit described above with reference to FIG. The difference is that a second inverter circuit 41 and a CMOS transmission gate 42 are used as the feedback circuit), but the other parts are the same, so the same reference numerals as in the 17th part are given and the explanation thereof will be omitted. That is, the notebook "N 2 is connected to the input terminal of the second inverter circuit 41, and this second inverter circuit 4
1 is connected to one end of a transmission gate 42 formed by a P-channel MO8 transistor T and an N-channel (O8) transistor T1° connected in parallel;
The other end of this transmigrating gate 42 is connected to a node N,
Connect each transistor T**T of this transformer connector 42. The gate of is connected to the input node Nl. The transmission gate 42 and the second inverter circuit 41 are connected to the inverter circuit 3 (hereinafter referred to as a first inverter circuit) as well as a delay hold circuit 43.
is formed.

According to the circuit shown in FIG. 4, when the input signal at the input node N□ is, for example, at a low level, the transistor T of the transmission gate 42 is activated.

When the node N is turned on, the delay hold circuit 43 keeps the node N at a high level. When the input signal changes from low level to high level, the above transistor T is turned off, and the other transistor T□ is turned off.

is turned on.

At this time, the output of the second inverter circuit 41 for feedback of the delay holding circuit 43 is at a high level, but when this output is transmitted through the transistor T4°, the threshold value due to the pack gate effect of the transistor T8° is As the output level increases, the output level decreases. As a result, interference between the output of the delay holding circuit 43 and the output of the first ratioless circuit 11 at the node N is unlikely to occur. Other operations are the same as in the previous embodiment.

〔Effect of the invention〕

As described above, according to the level detection circuit of the semiconductor integrated circuit of the present invention, it is possible to operate without receiving an input signal for a certain period of time after detecting the input signal, and there is no need for a clock pulse. Moreover, current consumption can be reduced. Therefore, it is suitable for use in an input buffer circuit for converting a TTL input deer level to an OS level.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the level detection circuit of a semiconductor integrated circuit according to the present invention, FIG. 2 is a timing waveform diagram showing the circuit operation of FIG. 1, and FIG. 3 is a circuit diagram showing the circuit operation of FIG. 1. TTL
FIG. 4 is a circuit diagram showing another embodiment of the present invention, and FIG. 5 is a diagram showing a level detection circuit of a conventional semiconductor integrated circuit. The circuit diagram shown in FIG. 6 is a timing waveform diagram showing the circuit operation of FIG. 5. Tyu~T9,. ...MOS) transistor, 11°1
2... Ratioless circuit, 3e41... Inverter circuit, 10... Delay circuit, 13.43... Delay holding circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 tl t2 t3 t4 t5 t6 t
7 t8 Figure 6

Claims (3)

[Claims] (1) P-channel MOS transistors T_1, T_2 and N-channel MOS transistors T_3, T_4 are connected in series between a high potential power source and a low potential power source, and each gate of the transistors T_2, T_3 is connected to an input node. 1, a first inverter circuit whose input terminal is connected to the drain interconnection point of the transistors T_2 and T_3 of the first ratioless circuit, and an output terminal and an input terminal of the first inverter circuit. connected between them, the conduction of which is controlled by the potential of the input node,
a feedback circuit that forms a delay hold circuit together with the first inverter circuit; and a feedback circuit that delays the output of the first inverter circuit and outputs the delayed output to the output node and also provides it to the gates of transistors T_1 and T_4 of the first ratioless circuit. A level detection circuit for a semiconductor integrated circuit, comprising a delay circuit. (2) The feedback circuit includes a P-channel transistor T_5
, T_6 and N-channel transistors T_7, T_8
are connected in series between the high potential power supply and the low potential power supply, and the gates of the transistors T_6 and T_7 are connected to each other in series between the high potential power supply and the low potential power supply.
a first inverter circuit, the gates of the transistors T_5 and T_6 are connected to the input node, and the drain interconnection point of the transistors T_6 and T_7 is connected to the input end of the first inverter circuit. 2. The level detection circuit for a semiconductor integrated circuit according to claim 1, which is a ratioless circuit of 2. (3) The feedback circuit includes a second inverter circuit whose input terminal is connected to the output terminal of the first inverter circuit, and an output terminal of the second inverter circuit and an input terminal of the first inverter circuit. and a CMOS transmission gate connected between the CMOS transmission gate and the gate of each transistor of the CMOS transmission gate connected to the input node. .