JPS6182276A - Integrated circuit mask design verification device - Google Patents

Abstract

PURPOSE:To obtain a device with expanding performance by connecting plural element extracting sections corresponding respectively to kinds of elements with a connection analysis section via a storage device. CONSTITUTION:The element extracting sections 21-2n are provided corresponding to kinds of object elements and one kind of the element is extracted by one element extraction section. In extracting an MOS transistor (TR), at first MOS TR is a common part between an expanded region 11 and a polysilicon region 12 and is defined as a part without contact holes. The element extracting section 21 extracts the MOS TR defined in this way by a graph processing, the source-drain region 13 of the MOS TR, a gate region 14, a boundary region (source-train terminal) 15 between the source-drain region 13 and the gate region 14, the representative coordinate 16 of the boundary thereof and a gate terminal 17 are extracted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides information on the type and type of each element from mask pattern data for integrated circuit (LSI) mask pattern design verification.
The present invention relates to an integrated circuit mask design verification device for determining constants and interconnection relationships.

(Technical background of the invention and its problems) Designing a mask pattern for an integrated circuit is an error-prone task that involves handling an overwhelming number of figures. Therefore, when designing a mask pattern, it is necessary to verify it.

Several methods have been considered for verifying mask patterns. The most commonly used method among these is the method shown in FIG.

That is, this method digitizes a design drawing of a mask pattern designed based on a logic diagram to obtain mask pattern data, extracts a circuit consisting of elements and their interconnections from this mask pattern data, This method verifies the extracted circuit through logic simulation, circuit simulation, etc. Another promising method is to compare a similarly extracted circuit with the circuit intended by the designer.

In either method, a circuit extraction unit that extracts a circuit from mask pattern data is important.

However, in the past, this circuit extracting section was configured with software, so there was a problem in that the processing required an extremely long time in the current situation where the circuit scale is enormous.

Therefore, it is conceivable to configure this circuit extracting section with a dedicated device, but in this case, there are problems such as an inability to expand when trying to handle many types of elements.

[Purpose of the invention]

The present invention was made in view of the above-mentioned conventional drawbacks,
The purpose is to provide an integrated circuit mask design verification device that is capable of high-speed processing and is highly expandable.

[Summary of the Invention] The stage information of an integrated circuit is usually summarized into two types: data for creating a mask pattern, that is, a glass mask, and data regarding the manufacturing process.

Therefore, by using these two pieces of data, it is possible to reconstruct the design. This process is called circuit extraction from mask patterns, and is an important step in design verification. By the way, the information included in the mask pattern includes elements and their connections. There are many types of elements included in an integrated circuit, such as transistors, diodes, capacitors, and resistors. On the other hand, when analyzing these connections, it is possible to reduce the process to a single process of analyzing connections between terminals of elements.

Based on these points, the present invention is characterized in that a plurality of element extraction units corresponding to the types of elements and one connection analysis unit are coupled via a storage unit.

Note that if the data used by the connection analysis section in the storage device section is all in the same storage format, it becomes possible to handle a plurality of types of elements.

〔Effect of the invention〕

According to the present invention, by separating the element analysis section and the connection analysis section, it becomes possible to easily add a new element analysis section when a new request occurs. Therefore, it is possible to improve expandability. Further, in all cases, only one connection analysis section is required, which is extremely economical. Also, as a result of separating the element extraction section and connection analysis section,
Each part of the device is converted to 111i, making it easier to increase speed.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, with reference to the drawings, a description will be given, in particular, of a circuit extraction section of an integrated circuit mask crotch verification apparatus according to an embodiment of the present invention.

As shown in FIG. 1, this circuit extraction section includes three storage device sections 11. '12.13 and a plurality of element extractors 2'1.
22. ..., 2n, an element connection analysis section 3, and a control section 4 that controls these.

For example, a semiconductor memory, a magnetic disk, or the like is used for the storage device units 11 to 13, but in order to operate at high speed, it is preferable to use one with a short access time.

In the storage unit 11, mask pattern data is stored as a set of closed figures for each mask pattern layer. Note that a closed figure is given by an ordered sequence of vertices.

The element extraction units 21 to 2 are provided corresponding to the types of target elements. That is, one type of element is extracted by one element extraction section.

Here, first, a specific configuration example of the element extraction section 21 that extracts MOS transistors will be described.

That is, as shown in FIG. 2(a), the MOS transistor is defined as a common portion of the diffusion region 11 and the polysilicon region 12, and a portion having no contact hole or the like. The element extraction unit 21 extracts the MoS transistor defined in this way by graphic processing, and extracts the source/drain region 13, gate region 14, source/drain region 13, and gate region 14 of the MOS transistor shown in FIG. A boundary portion (source/train terminal) 15 where the two contact each other, representative coordinates 16 of this boundary portion, gate terminal 17, etc. are extracted. Further, the electrical parameters of the element (for example, the dimensions of the transistor) are calculated in a parameter extraction section (not shown). These results are stored in the storage unit 12.

Next, the specific configuration of this element extraction section 21 will be explained based on FIG. 3. That is, this element extraction section 21
The diffusion layer pattern file 21 and poly9112 layer pattern file 22 of the storage device section 11 are input, and the polysilicon wiring layer pattern data file 23 of the storage device section 12, the gate pattern file 24 of the MOS transistor, and the MOS l-transistor terminal are input. The outputs are a boundary line segment file 25 shown, an element file 26 including representative coordinate points of each element terminal and pointers to individual elements, and a diffusion wiring layer pattern data file 27.

This element extraction section 22 is roughly divided into two parts. The first half is a part for efficiently extracting pairs of mutually related patterns, and the second half is a part for recognizing MOS l-transistors.

The two input pattern files 21 and 22 are:
This is a file sorted by the lower left point of the pattern data. The pattern at the lowest left point is stored in each pattern data register 28,29. Pattern data register 2
From each pattern data stored in 8.29, only the lower left point data of the diffusion layer pattern and the polysilicon pattern is extracted by the lower left point coordinate extraction circuit 30.31 and stored in the register 32.33.

- Register 32. , 33 are compared by a lower left point coordinate comparator 34, and the leftmost pattern is selected. When the diffusion layer pattern is at the bottom left, the output of the bottom left point coordinate comparator 34 is II I 11.

Processing target pattern pair extraction circuits 35 and 36 extract pattern data from each pattern buffer 37 and 38 from the pattern data register 28.
．． A group of patterns related to 29 are extracted. The pattern data deletion circuits 39 and 40 include pattern buffers 37 and 38.
The pattern data that is no longer needed (no longer a target) is extracted from the pattern data file 23.27 and outputted to the pattern data file 23.27.

The common portion and boundary extraction circuits 41 and 42 extract the common portion of the polysilicon layer pattern and the diffusion layer pattern,
Furthermore, the boundary portion (corresponding to the source and drain terminals) of the common portion (corresponding to the gate pattern) is extracted and stored in the gate pattern file 24 and the boundary line segment file 25.

The representative coordinate extraction circuit 43 extracts representative coordinates as shown in FIG. Store the data of.

Pattern addition circuits 44 and 45 are non-common part extraction circuits 4
Considering that the pattern data extracted in step 2 may be subject to processing again, the pattern buffer 37
．． 38, the pattern of the above-mentioned non-common parts is returned.

Note that 46, 47, and 48 in the figure are multiplexers for switching data as necessary.

The above is a description of the element extraction section 21 that extracts a MOS l-transistor. However, when extracting a diffused resistance, the resistor main body 5 shown in FIG.
1 is taken out, and a contact resistance pattern 52 is embedded in consideration of the contact value.1 Here, the terminals 53.
54 can be calculated by dividing the contact resistance pattern 52 into meshes and using the finite element method or the finite difference method.

The element extraction section can be similarly configured for other types of elements. Each data from these element extraction units 21 to 2n is stored in the storage unit 12 via a bus.

The storage unit 12 stores extracted data from the element extraction unit, but in this case, the details of the stored data differ depending on the type of element. However, as shown in FIG. 5, this storage unit 12 stores common data in a data structure consisting of the X and Y coordinates of a terminal and a pointer to an element table in which elements including the terminal are arranged. ing. therefore,
A unified interface with the element connection analysis section can be implemented. Inside the storage unit 12, the data shown in FIG. 5 is sorted by coordinate values or expressed in an appropriate tree structure, so that the next element connection analysis unit 3 can process it at high speed.

The element connection analysis section 3 extracts the connection relationship between elements by investigating the inclusion relationship between the terminal coordinates and the wiring pattern shown in FIG.

In this way, according to this embodiment, the element extraction units 21 to 2n for each element and one element connection analysis unit 3 are connected using a common data format, and a unified interface between the two is realized. Therefore, only one connection analysis section 3 is needed. As a result, the unique processing of each part can be performed in a distributed manner.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a circuit extraction section of an integrated circuit mask design verification apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating a method for extracting MOS transistors in the circuit extraction section. , FIG. 3 shows the MO in the circuit extracting section.
A block diagram showing the element extraction section of the S t-transistor, FIG. 4 is a diagram for explaining the method of extracting the diffused resistance in the circuit extraction section, and FIG. FIG. 6, which shows the format, is a flowchart for explaining the mask design verification procedure. 11... Diffusion region, 12... Polysilicon region, 1
3... Source/drain region, 14... Gate region, 15... Boundary portion, 17... Gate terminal, 51...
・Resistor body, 52 ・Resistance pattern, 53.54・
...Terminal. Applicant's agent Patent attorney Takehiko Suzue Figure 5 Figure 6 Eye Ring Diagram Fus7/f7-n1tsu1
1411 times 9'mas 7th edition
Collaboration tour
Dry'-Vertical Izo Swim 7f7-Elementary U3 Road Yuzugi

Claims (2)

[Claims] (1) In an integrated circuit mask design verification device that extracts element types and interconnection relationships between elements from mask pattern data of integrated circuits and performs mask design verification, the integrated circuit mask design verification equipment is provided for each type of element, and a plurality of element extraction units that extract elements to be extracted; a storage unit that stores each element information extracted by these element extraction units; and a storage unit that stores interconnection relationships between the elements from the element information stored in the storage unit. An integrated circuit mask design verification device comprising a desired element connection analysis section. (2) The storage unit stores information related to connection analysis between elements from each element extraction unit in the same data format among the element information. The integrated circuit mask design verification apparatus described.