JPS6182272A - Vector processor - Google Patents

Abstract

PURPOSE:To use a large memory space by providing a storage managing circuit using an expanded storage as a base in a vector processor and using the storage management circuit so as to assign the large scale memory space to the user. CONSTITUTION:An instruction stack has distinguishly instructions for each processor so that three kinds of processors: a paging processor 107, a vector processor 102 and a control processor 101 are processed in parallel at the same time. Further, a decode processing managing device executes plural decode processings for instructions of the said instruction stack in time division. Since a logical device is provided and a program existing on an expanded storage device 108 used in the partial set of the program is executed by plural main storage devices 104, 105 and 109, the area on the expanded storage device 108 used in the partial set of the program is loaded and stored to a designated main storage device.

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a flat file processing device, and in particular to a flat file processing device equipped with an extended storage device suitable for large-scale computer science calculations.
The present invention relates to a processing device having a processor configuration. Background of the Invention 1 Today, in the field of scientific and technical computing, large memory spaces (several 100 MB) are required due to high-speed calculations. Assigned to
In addition, it is impossible to realize Sosai 1 using only the main memory device due to cost. Tokujibe'71. Since a file processing device is required to be faster than a general-purpose machine, it is difficult to reduce the cost of using a high-speed memory element. In order to satisfy users' demands for large-scale memory space and cost, supercomputers equipped with a large-capacity expansion storage device outside of the main memory have been announced (Kodaka et al., [Nikkei Nirenor). 1° [1 Nix J N, q
314, P, +59-184, Nikkei McGraw-Hill I
! 183). This extended storage device is 1-storage device is different 1
1. Page (4KB), not word-level access
By medium continuous access, flRNOOOM barr
g) 7 seconds 7)'-Tano data transfer speed has been achieved. This data transfer speed is 11 times higher than the data transfer processing speed on the main memory of a general-purpose computer, but since it is a data transfer speed that can only be achieved by continuous access of large data blocks, the expansion storage is directly connected to the vector processor. However, it is not possible to realize a large memory space of several hundred MB through user vector processing. [Object of the Invention] An object of the present invention is to equip a vector processing device with a memory management circuit based on expanded memory, and to
) allows the user to allocate a large memory space with τ, and uses a large memory space.
t7Ff rl a Beg1Hel processing device that can perform 4 arithmetic
It is about doing E. ``Summary of the Invention'' The present invention realizes parallel execution of data processing for one set of data in a plurality of main storage devices, a paging processor, vector processing 17, and each processor using a VEG1H processing device.

[
7, a large-scale program existing in the expanded storage device is executed on a plurality of main storage devices each having a smaller capacity than the expanded storage device. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the basics 1i1' of the vector processing device according to the present invention.
f IR, -1 control processor 101, vector processor 102, paging processor 107, and storage devices 10/I, 105, 109 . Expanded storage device 10
8. The switching circuits 103 and 106 are configured. A program that specifies vector processing is written using object code with the following structure. When a set of vector and scan instructions that make up a program specifies processing operations for data in a memory space that is different from other sets, the second set of instructions is called a segment. The data space pointed to by a set of instructions is called the local memory space. Many segments and local memory spaces defined in this manner can be found in scientific computing programs. For example, in the o-loop as follows, D○ 100 1
=1. N +00 A (T) = B (T) + C (T) r') O The sequence of vector instructions that constitute the loop is a segment, and the arrays A, B, C and r) 0 control variables T, N are The memory space it occupies is local memory space. Thus, programs can be defined by segments and local memory spaces. According to this definition, sufficient processing is necessary for program execution. Regarding the program PL in Figure 2, a-C segments are shown, T-a is an instruction to create a local memory space in the main memory where the segment will be borrowed, and STa is an instruction to create the memory space in expanded storage. Indicates instructions to be stored on the device.The same applies to segments a and b.A program consists of segments that specify data processing, local areas,
Although a program can consist of a memory space and instructions that manage that space, the program itself is also defined by segments and local memory space. This will be explained with respect to PIl in FIG. Here, in STb, the data processing is STh
Assume that it can be divided into before and after. This assumption is logically constructed based on the assumption that the program executes each component segment in order, so it is valid. STb
If the program division at the point is line -], then ① an instruction to rope ink the instruction group from the a instruction to the STb instruction onto the main memory, an instruction to store the instruction group in the extended memory 'JA location, and the progera 11 By defining instructions for instructing the execution of 1), the programmer 11 can be reduced to three types of operation definitions: loading, execution, and steps 1 to 7 of the program itself. This reduction is shown in program PI of FIG. The condensed program shown in 2 is a relatively small memo +
It can be held in one space until the execution of the program is completed. For scientific and technical calculations. A program cannot process itself, but if it performs more complex data processing in the future, it is possible that the program will transform itself. In such a case, the desired processing can be performed by placing an instruction for transforming the program itself next to an instruction for loading the program into the main memory. P2 in FIG. 2 shows the structure of a program that transforms this program itself. In P2, the α portion is a segment that deforms the procla 12α portion (this is composed of segments a and b). JTi, tb, as shown in Figure 2, the part that loads, edits, and stores the program into the main memory [Pro/7 RAM Kernel] , the portion that is subject to quotation by the Progera 11 kernel is called ``Program Bote, I''. In the vector processing device of FIG. 1, the program shown in FIG. 2F) is processed as follows. The controller 1 is initially placed on the expanded storage device 108. When the vector processing unit is started, the controller 1 is
The program processor 101 starts the paging processor 107 and loads the program kernel portion of P7 in FIG. 2 into the main storage device 109. After the T1 roll processor lot receives the rope ink completion report for the processor set 107,
Execution starts from the first instruction of the 01-digit program kernel section. The first instruction of the program kernel part is Progera 1
Since this is a command to load 1 body 7fα to the main memory, the second command loads the program [1η to 11] from the expanded storage 108 to the main memory 109.Next, the control processor 101 The program body loaded into the main memory 109 is modified according to the instruction from the section α and the next segment EX and E C indicate the instruction processing position of the control processor 101. ) is rewritten and control is transferred to the body of the progera 13. This operation is similar to an unconditional branch in a general-purpose computer. Since it is an instruction L a to perform a herotation, the control processor 101
Page processor 107. An instruction is given to the switching circuit 106 to load the local memory space of segment a on the extended storage device +08 to the main storage device 104 or 105. In this second example, it is assumed that the local memory space is allocated to the main storage device 104. Control processor 101 then executes the instructions in segment a under the control of cpsw. Assume that a VEG1HELL instruction appears in segment a. At this time, to Con 1, "1-Le Processor 101
The vector processor I n 2 and the switching circuit 103 are activated and instructed, and instructions are given to connect paths so that vector processing can be performed in the main storage device 104 on pairs 1-4. The vector command is read from the main memory 109 by the processor 101 and sent to the vector processor 102, where it has already been loaded into the main memory 10'I'. Vector processing is performed on the local memory space of ; While the vector circle is being executed in the vector loop 102, the -1 control processor 101 has no command to wait for the completion of the beta 1 hell processing immediately after the vector 1 hell instruction.
Executes the next instruction. Assume that the next command is a rope and ink instruction for the local memory space of segments l-h following segments 1-a to the main memory. At this time, 1 setter 101 switching times 7fj I n 6
, instructs the paging processor 107 to allocate the local memory space of segment b of the extended storage device 1081- to the main storage device 105. Gono r+ -=-1: The operation can be performed at the same time as the vector processing raccoon. In order to effectively use this function of simultaneous execution of row 1 operations to the main memory in the local memory space and the parallel processing, it is necessary to optimize the program body of the object code. The program 11 body part on the extended storage device initially has internal/structural information as shown in Figure 3a.In the program of Figure 3a, each segment executes its segment i. It has an instruction to allocate the local memory space necessary for the main memory to the main memory, and an instruction to store the result of the processing specified by the segment to the expanded storage. Since the raw processing unit instructs the sequential processing of loading the local memory space to the main memory, processing the data, and storing the processing results to the extended storage, performance cannot be expected to improve.The control processor 101 and the paging processor 102 In order to enable parallel operations between the two, the instruction string is divided into the following four types: ■ Instructions for data processing in the control processor (hereinafter referred to as C instructions) instruction (hereinafter referred to as P instruction) (j) 1 of the instructions (hereinafter referred to as CW instruction) to check the status of the paging processor in the control processor. It is loaded into the main memory 109 in FIG. It is determined whether the instruction is held in the control processor or sent to the paging processor.If the P instruction is held in the control processor, for example, if the paging processor is busy and the P instruction is If it is not accepted, if you wait for the control processor or page processor to finish, it will cause a serial state in the control processor's instruction decoding process. Even if the P instruction cannot be executed because the paging processor is busy, if the next instruction after the P instruction is logically executable, the next instruction is executed and the busy state of the paging processor is released. It is necessary to immediately execute the P instruction in the execution pending state.In order to perform this type of instruction overtaking, the instruction decoding process is divided into two systems of C9P instructions.However, the instruction execution of the control processor Since this cannot be executed conceptually like the code in Figure 3a, the code processing of both the C and P systems is time-sliced 1, and the commands are controlled to be executed alternately in a time-sharing manner. . With this control,
After executing the C instruction, the P instruction is started at a certain timing, and when the paging processor is released from the busy state, it is possible to immediately send paging information to the paging processor. Only L・
, this time-division decoding processing does not include any synchronization processing in the processing of instructions of both systems. For this reason, for paging as shown in FIG. 3A, a case may occur where the operation of a program that specifies serial processing is different from the one12=1'PI1-fJ-. For example, the third
In Figure a, when the P instruction ■, a is executed, if the time-sharing tick 1-1- processing is performed, the data processing of Se Gumen [-a starts even when the La instruction is not processed. It's been done and it's gone. In order to eliminate such inconvenience, CW. PW series instructions are required. Add this series of instructions [
7. New object code generated as shown in Figure 3 (1) on the right. The object code in Figure 3 assumes the following processing. (1) The paging processor has means for distinguishing between the local memory characters and the main memory to which they are to be loaded. -) When loading of the local space is completed, information indicating to which main storage device the data transfer has been completed is reported to the control processor. ) The main memory whose local memory space is ``l-'' is commanded as 1.2 and used according to the order of 2. 5 The ν column is an instruction for the 11 control processor. However, the instruction for the paging processor is also
Leverage processing is performed by the control processor. The object code having the structure shown in Figure 3 is executed as follows. First, the L a instruction in the μ column is decoded, and the paging processor is instructed to start transferring the local memory space required for segment a. At the next timing, TJn of column ν
The Ljll instruction is decoded, but since this instruction waits for the completion of data transfer to the main memory (1),
The next segment a in column ν is not executed. After a certain timing, the r-b instruction in the μ column is decoded. If the paging processor is busy at this time, this L b instruction will not be executed and will be held on the instruction stack. At the next timing, control shifts again to the ν-column command. At this time, the TJntill instruction is executed again, and the control processor waits for the paging processor to finish. When the paging processor completes the transfer of local memory space for segment a, the instruction on the instruction stack, ie Lll, is immediately executed when the control processor's control is over the instruction in the μ column. -1 n1
~ When the control of the roll processor is in the command column 1, TJltjll is executed, and the 2(h part is immediately completed L7
From the next timing, secnont a will be executed. In this state, at a certain time, the instruction in the μ column will be executed, and at the same time, the instruction in the ν column will be executed. When the instruction in column 71 reaches the W instruction (see Figure 3 i), μ
The decoding process of the instructions in the column is stopped until the Rel instruction is detected in the instruction column of the ν column.1. do. After the data processing of 1 cell or 1 cell is completed 1-2, the order in which the target local memory space is transferred to the extended storage device is determined by the W command of the worker. can be guaranteed. −
jr, ν column instructions are TJnti, ] after the Rel instruction.
2 instructions (I), the transfer of the local memory space to the main memory (2) has been completed, and if so, execution immediately moves to the next segment b. In Figure 3, IT is in column ν.
A series of n white 1 series commands or E is issued, but this causes S in the p column.
Since the instruction to transfer the local memory 11 space in the same main memory like the Ta, f-, and c instructions is not performed, the completion report from the paging processor = 15- corresponds to the fact that two instructions are sent at the same time. ing. FIG. 4 shows the busy status of the roll processor and paging processor in the object code 1 having the structure shown in FIG. 3 when it is executed by the object/raw processing device of the present invention. In Fig. 4, the dotted line represents 1 cell, way i, and time. As is clear from Fig. The control method between the control processor and the paging processor shown in L7 above also holds true between the vector processor activated by the control processor and the control processor. However, the vector processor has data processing characteristics that make it difficult to control the processor weight.The structure of the object code when this vector processor is controlled is described below. It is performed only within one segment 1~, and is not performed across multiple segments.If you think about it in the simplest way, it will have a structure like that shown in Figure 5a.
In FIG. 1A, the instructions in the ν1 column represent the vector instructions IJJ, , +l. Instructions other than the X little instruction are hereinafter referred to as scalar instructions. Control 1-role "This is an instruction to control the processor that is generated from the 1st processor, and a minimum 1st-order instruction sequence is required. Setup instruction to prepare for t2 > 7 reset command (called J゛〕, lower EX input 7p). -J, lower TVP). According to the three types of instruction system in 2-], =+n1-role ``One second instruction de:1-de changes the timing logic-and controls the vector processor. becomes possible.
Then, by the instruction shown in FIG.
Considering the operation of the processor, as is clear, the control of the processor is
■When the P instruction is reached, at that point the data processing of the =1-[1-le processor ends], TVPJ',
, the following scalar processing a-instruction sequence cannot be executed. This is the invalid time caused by adding one sensor to the control processor. is further subdivided into the following according to the type of data processing. Processing (hereinafter referred to as a7)
Processing) (Processing that must be performed after AI vector processing (hereinafter referred to as a, processing) r7j) Command to start checking the completion of solid 1 to 3 processing (hereinafter referred to as 5TVP) Condolences) a, processing, a4 processing Command indicating the boundary of (hereinafter referred to as Bn
rTNr1) When segment-a is reconfigured by the instructions shown in the above classification, Figure 5 is produced. The control of controllers 1 to 2 and the vector processor is as follows:
:fll series of instructions = 1 n i [] - le processor τ
Executed 1171. The EXVP command is = 1 nt ``1-proceno square τ child-1-de 41. Vector processing - move, Vegt I +, / life sequence is activated 1 The vector 1 is read out from the main memory 109 (see Figure 1) via the
Day 1-1. s i+execute]. a
. The series of instructions are asynchronously leveraged and executed by the control processor set r1.
By the T■P command, the phase of :I Trolp [1 senomasu child:"-Dosarkurke 2-] is 11 times before division.
In the first step, the data processing in the vector processor is completed, and the check is made as to whether or not the second σi ”
7. When the two series of commands are executed, the two are defined, and occupy the time between each other. If the cheater processing for 1 set is completed, the first phase is turned off. In the processing of the a7 instruction, if the BnuNn instruction is detected, the second phase disappears. By introducing the two-way de:1-toface, it is possible to check the completion of vector processing and at the same time execute part of the processing of the scalar instruction. -Loop [“Invalid time” caused by adding a vector processor to one setter]
can be minimized. 1! L I:, Although we have discussed minimizing the ineffective time for terminating solid 1-hell processing, exactly the same argument can be made for vector processor activation. Next, consider the location of the program. As mentioned above, the locations of the progera 11 and data are defined by the real addresses of the extended storage device l-. Naturally, the data processing procedure of the program is also described by the location. On the other hand, when loading the local memory Il space to the main memory and performing two data processes on this loaded new space, if the previous location makes it impossible to perform two data operations,
Set the local memory space to any address in main memory 1-+ -I
The control processor sends information indicating whether
20 = local/memo 11 space rl −1 command to deni 1−
``1 nt ``J-rupu''
1 set (Huff processing, vector processing of vector processor 1-F-1) Performs the memory access at 1 nos relocation that occurs. The 2nd located at 1 nos indicates the real address of the main memory. Therefore, 1 -torped processor, Vector Palp "7 de Inosuri""One -one shyon mechanism" It is possible to execute a program in the local memory space 4: The above discussion is based on paging program r: 1 session's local memo 11
It is only concerned with space management, and not with the structure of the local memory space itself.Vector processing involves performing uniform data processing on a specific data group, so scalar processing As in [order of processing]
Regarding the above data group, it is not necessarily necessary to guarantee the elements in the data group. Considering the following 110 loops, nO1001=1. ]OOO A (I) 2B (■) 10C (■) 100 C0NT To I TJ EΔ To 91~R elements in the order I+ 2+ 3+...R] Need to be calculated, 1 +' 3+ 2+ 4 + 5
+... may be the order. m = DO small loop described above In the same segment, there is a Q loop as follows, which is traced. nn 2nOT=1,999,2 n (T') = l"3 (T)*C(T')2 o
n CoNTT NTJE The latter DO small loop is different from the former loop. Access to C Beta 1 Hell is not continuous but discontinuous. Veg1Hell processing is a process that allows the pipeline arithmetic unit to perform take processing without interruption to improve processing speed.
It is more efficient to place operand takes at consecutive addresses than at non-consecutive addresses. If the B solid 1~le element is located as I 12131, the second [I cation is suitable only for the former solid 1~le processing of D○, but the former is suitable for the latter D○ processing. It's not quite suitable. but,
I,3,2.4,
5.7.6+ 8+a) yo-), the latter I]
○Kuru principle (Even in 2, it is continuous 7' nose: 1, take processing efficiency is 1 -. In no processing, the order of takes is guaranteed in vector] le processing. However, since it is white without access, the data processing efficiency will be lowered and the data processing efficiency will be lowered. If lIH exists, divide the array into m*n subsets by using m*n's fI1 plus 1]. Even if you perform an operation like ';jlt I#lnear',) you can separate the subsets that are pointers and separate them.
·stomach. The second separation operation L; The access to the old zowa within 5 minutes in 1 part is 1:17. fI: When loading the local memory space 1'Z in the extended storage device to the main memory (-1i IFi), it is recommended to rearrange the subset of the array in In the second step, we optimize the tiVt structure of the local memory space, and the plateau f of vector processing.
You should be able to do 2k. As f'8', the processing distribution is performed in 1 seso vectorp and 1 seso sweet, and the high speed of the vector processing device can be further improved. Optimizing by set relocation, loading the first subset that is not accessed into the main memory L, does not mean that the segment is not accessed.Loading the subset that will not be accessed into the main memory,
If not, the main memory 8 size will be smaller, but when writing the local memory space to the expanded storage device, the portion of the main memory that has not been accessed will be loaded prior to the write operation. It is necessary to read from the expanded storage device, perform the jψ operation for redistributing one subset, and write the result to the expanded storage device. Access to the expanded storage device is different from access to the main storage device, and is fast only when one type of access is continuous, so successive writes to the expanded storage device occur alternately as shown above. , the take transfer speed will drop significantly. Therefore, when a segment accesses and loads a subset of the missing local memory space into the main memory and writes it to the local memory space a: lij', l'jf3, the main memory Tongue 1.4! l1f
i: Access and rearrange part 1 j game! Perform the operation 11) to transfer the data to the storage device 1. J″l, 1 Perform segment processing of 1 graph 11, limit the information + lI of the main storage device rt to the local memo 11 space, or -) create memory space by rearranging a subset of the local memo + 1 space. To optimize the segment processing of
The large memory space required for each program's execution is 6 U21. The outline of the preprocessing part of the instruction decoder of fj control [1-rou/'r+set] in the Vedator processing device of the invention is [1]! This is Figure 7. In FIG. 6, the command is sent from the main memory 109 (see FIG. 1) to the flip-flop knob (hereinafter referred to as FF) 600 via path 650.The command of FF6001 is sent to the command management circuit. 601, the pacing processor ``J processor'', the T1 nt ``1-le processor,'' and the 91- loop ``l processor 1'' are classified as commands for the pacing processor 7 through the FF 602 for timing adjustment. r soting circuit 603
The instructions for the pacing processor are sent to the instruction stack 604, the instructions for the ML control processor are sent to the stack 605, and Betta 1 help [The command for 1 set is entered in the status 606. 608 is the command),
This is a circuit that manages instruction transfer in Taraino 60/l)
, the circuit operates during a specific phase defined by the phase generator 1 notaro 07. The following two phase r minks are called A face, and the commands entered in the stack 304 are 1.
The instruction enters register 609. The instruction 1 register 609
The above instructions are child-coded by the decoder 610 and classified into one local memory space rotor or store instruction, a wait instruction, and its pool instruction. In the case of a rotary/S1-A type instruction, use the selector 12-digit path 51, in the case of a wait instruction, use the path 652, and in the case of other instructions, use the path 653.
Select. -Jj Paging processor 107 (see Figure 1) state (1 pass n 5 ・I l '+ff4 L
TE F F 61] 11: (Stupid EIF main 11τ ai) 6'''2 paging group ``1 set or 1' sea I
I 'p is F F t; 11 The force state is "B" and 1.
Even in the case where τ is smaller than τ, it is assumed to be −”n”. In addition, the stack management circuit ('in8 ni ke pass 6!' i 5 right) [,
τ Opposite transition extrusion information 1"!, +', 41romono-oro-"l -l:・S For 1 to 7 series commands, selector 6
12 (''puff, [) 51 [355 connection right, so
Page solip "1st...) 107 is busy tlj
The l111, o-do or stgo' instruction remains in the instruction 1 register 609F. Pacisogep ``I'm busy at 107. I'm busy now, pub 651 and 6.''
The instruction transfer permission is given to the stack management circuit 608 via the path 65 (11), and the local memory space σ) read or store instruction is transferred to the paging processor +07 via the path 65 (i'j;r'Ii1). :g. Pagen at 1')) The command operation for the 1st setter 101 is related to the RE1 (release) command of the 1st setter 101, so it is The processing will be explained below.
After entering, the stack management circuit 614 manages instruction migration. The stack management circuit 614 ke phase shene 1 notaro 07 operates when A fue (generates 7 AIDS other than Z) [-1 (J!J, this phase below is called B face). Receive the type of instruction transfer extrusion instruction through paths 657 and 658. When there is no instruction, the stack 605 is transferred every time the instruction B phase is generated, and it enters the instruction register 613. On the instruction register 613 The instruction is decoded by the decoder 615, and in cases other than the R, E, and L instructions, '1' is set in the FF616.
This indicates that the control processor 101 is currently executing a segment of the program. TE:】-T6
15 is RET, when the command is decoded, FF615 ke II
n Reset to D. Main storage device f'ff in Figure 1
1ll') 4,105 consider the following state. (1) The local memory space in the main memory is [1-dogo11゜11soll-rl-loop [1 set and vector prostheno or l', %, river hit (I knee:) tW': 'E memory (=!21F' paging to f-1)
The paging processor 107 is in the state of the storage device 1i'! - The report is sent to the control processor 101. In Fig. 6, the path 660°6 (through 51 τ sol +) l main memory!X
Ji 1st page 10/l, 105 condition report is covered J't
, FF 620, 621 to 1 [Terasa Saisuruichi FF6. l! If the pagen'nozu Royale 107 is in the generate state, the 1st shift of pagen'nozu Royale 107 is in the generate state, 1"1 is in the 1 note state.If n 14. When the i + instruction is decoded, an instruction is given to the selector 622 to adjust the state of the main memory device 104 or 105, which is the main memory device 104 or 105, and the state of the FFI'i2Q cross 621 is changed to pass. 6
The data is sent to the selector 23 via 62v and 663. Se1 Noritaro 2, i'r-keTTntjl type command, pass [;6411111, 1dr+Iil type 1゛J
, 1itR is applied to the path 665 side when the instruction is outside. If the instruction LTntill is decoded by the decoder 615 and "]'" is located on the main storage device 104 side, one concatenation of paths 662.66/l and 657 is performed, and the FF62
A state of 0 is sent to the stack management circuit 6]4. At this time, if the content of the FF 620 is "1", the instruction transfer process of the stack management circuit 614 is pushed out 1 (, instruction register 6
13''-, the TJnt and jll instructions are retained. This instruction retention process is performed until the paging processor 107 becomes ready. Paging processor 107
When the is in the ready state, instruction transfer is performed, and pass 66
The instruction is sent to the next-stage instruction decoding section of the control processor 101 via 7. For songs other than those in the Until series, the selector 623 selects the path 665 side, so no command transfer instruction is issued to the stack management circuit 614.
Instructions are sent out on path 667, t: regardless of the state of paging processor 107. Returning again to the explanation of the instruction code processing by the paging processor 107. If the command is 09 to 11 engineering r1, the command is east, 7
-1-ta [;According to the instructions of 10, set 1))) Taro 12-digit pass ri! ”i:! Δ selection IR 2nd) Therefore, 11-1
To [1-Le Brosset...) Order for Sweet 101 RE■
, issued L@, limited to 1 set of 10
In the state of waiting for 7 commands, the command is issued at the end of segment processing, and the processing within one local memory space is 1r1-2! -f, 1 space is included in the extended storage device 108.
t)) It is guaranteed that the Into relationship is 11. The Beto 1 Tor command passes through the Su (Sochin 1) circuit 603. Enter stag 60G, manage the second stack Vf
I M 63 n'7: $+ Z+, via the stack management circuit 3' fl 63 Q path 670)
7 1-le instruction read request signal from 102 (see 11th section 1)) 1-le instruction read request signal (7)
) to 47' (Jl/Order sent to Hepuff 9711-5 each pukso') Management circuit r; Q8, 614.6' 30 Enter command or start +7. Of course, it requests the instruction management circuits 601 to suppress instruction sending 11- through the OPUS 8n, 681, and 682. The instruction management circuit 601 checks the relationship between the instruction in the FF BDO and the sending extrusion instruction, and determines that the stack requesting continuous instruction processing and the instruction type in the FF 60 Q match. In this case, a disable signal is sent via the path 683 to interrupt the instruction successive processing of the main memory @109.]
] to the instruction reading circuit of the 1-roll processor 10. FIG. 7 is a general block diagram of the post-processing portion of the instruction differential 1-der of the controller 1 roll processor. Instructions for control processor 101 pass 66
7 to the stack 701. The stack 701 of : is managed by a stack management circuit 702 to transfer instructions within the stack. The instruction transfer operation is the sixth
This is performed by the B phase output signal of the face generator 607 shown in the figure. It is assumed that the phase signal is sent to the circuit block of FIG. 7 via path 750. Cell
In the initial state, the Tsukutafu 03 selects the path 751 and inputs it. Therefore, the stack 1- is shifted in synchronization with the instruction number B of the stack 70]:J-, and is stored in the shifter 704 of the instruction 1. Instruction 1 = 1.' shift 97 CI, 40 commands are a lever
Tough 05 decoded JI, Vector-1 "1 setter activation instruction (FXVPi) Vector processor status check start instruction (STVP), ON, t11τ execution τ instruction as well as t11τ execution τ instruction IF. Commands that indicate the field (11nT■Nn) are classified as: F X N, 7 r' or S T V r is decoded 11
In the case of It is decoded by the second stage 708 and
The start or check information of the 1 setter 102 is written with double lines to identify the 1 + Q path 75 4 (Tl MA) throat signal order or 1 child - 9 signal 6. ) 4-year-old, required for Betatoru fr + Sessa 102*,,! W can't be shown. 2 no 1 yen, lever 1-
At 705 pm, -r Frr 7 n q” l
” and sent to the selector 703 via the second forward tilt path 755. On the other hand, the B7 and r signals sent via the path 750 are sent to the second forward tilt generator 710. Enter the
The B phase is further divided into C, D phase, and r phase. Both faces C and D are not generated at the same time. Here, the first C phase is used to decode the second instruction on the stack 701, and the D phase is used to decode the second instruction on the second instruction register 707.
It is assumed that this is used for decoding processing of XVP or 5TVP instructions. Now, if the second instruction register 707 is
Suppose that the P command has been stored (8).At this time, F
The FF70 is generally set to F709.
The output of signal 9 passes through path 755 and operates selector 703, which selects the C phase signal on path 752. On the other hand, the activation or check information sent to Beta 1 to Luprosenosa+02 acts on the vector processor 102.
．． The response is sent to the FF 71 via a path 756. Here, the f direction of FF7]] is LL D II
A value of 1'' indicates that the vector processor instruction was successful, and a value of 1'' indicates that the vector processor instruction was unsuccessful. FF7
1 The value of 1 is sent to the comparator circuit 71;
I'm sorry for the inconvenience. - and '7' - draw the following hypothesis. Sele 9 tough 14 ke initial stage:
Ikfl? Assume that the τ-th path 753 is sent by Tatsumi tR, and the path 75'3 is I) 7E, , (S signal is sent I), and SatI is sent. ! Hdi'/timesvII7 1 2 Force output is pass 757
Through and with. If the logical product of the 1 x 4 signal and the AND circuit 713 is t+.The content of FF 711 is 0''', then -) n77, (When S, that is, E
The S T V P command is actually 1:? Set FF709 to ``0'' with the tied mini knob that you turned.
If F 7 0 9 goes to reset 1 to 11 0 11, select the setter 03 path 751 again ↑H, and decode the instruction 1 at B7 and rs as in the initial state. Contrary to 1, as a result of calculating the AND circuit 713τ, FF 709 or 11 is set i'L
l'i", 40 go, 1))
Select 2 [-, Se1notenota 714 (Sat pass 75 pieces I
I choose. That is, in C'7 Ace, the instruction stack is 7 0
] In the D phase of 111, execute the command transition of -1-. 07.1-(7) EXV
P-straight S T V Executes P command processing. During the C phase, the instructions in the instruction stack 701 do not include the EXVP or STVP instructions. Kowakebe'no F.
This is because there is no logical meaning in starting up the vector processor 102 after starting up the vector processor 102 or checking the state of the vector processor 102 immediately after starting up the setter 102.
The vector processor ν102 is activated by XVP, and after several timings, the vector processor 102 is activated.
If you want to check the status of , you need the T3 0 U N r1 instruction immediately before the S T V P instruction. Under this condition, the following explanation holds: During the C phase, the decoder 705 and the instruction I register 70
4 decodes the 11 command and connects paths 758 and 759 by switching circuit 706. Follow-], C
In the phase, the instruction is transferred from the instruction 1 nozzle 704 to the third instruction 1 nozzle 715. Third instruction register 715
J- instructions do not include EXVP and STVP instructions due to the above conditions. The instruction of the 31st register 715)1 is analyzed by the decoder 716. Only when p, nTTNn instruction, FF7 1 7 is '1'''.FF7 1 7 is '1''
The selector 7141, the opus 751'', and the like 757 are connected via the path 760, which connects the selector 7141 and the selector 757 to the cell 1 through the path 760. At the same time, the stack management circuit 702 is instructed to move the instruction. This place T! From H d. After the T'lnTITrl instruction appears, C, D7,
EXVP.7 in the second instruction register 707. ST
The VP command is executed. Also FF7 1 7 or Pa 1
” or when the stack management circuit 702 can no longer stack a new instruction on the instruction stack 701, the OR circuit 718 outputs the logical sum of ! 'N is 11th rolep L1
In the first stage VfI (FIG. 6) of the first stage of the set 101, the reset of the FF 717 is carried out through the path 658 until the 1 node pump of the vector processor 102 reaches II n 11. Yes, the reset of the 7+tosopf 1 block 717 is performed through the Y repass 761 to the output of the AND circuit 7]3.
In cases other than the TJ ND instruction, the FF 717 is not set to 'BI', and the instruction of the relevant I/O sister 7151- is sent onto the path 762 at the C phase timing. A path 762 is connected to a control processor circuit that performs instruction decoding processing similar to that of a general-purpose computer. Next, using FIGS. 8 to 10, we will explain the data transfer operation from expanded storage to main memory by the paging processor η(
a. In the paging processor 107, a subset of the local memory space is generated and rearranged using the local memory and the mark 1 register. Local memory is a memory that temporarily holds data when loading data on an extended storage device.The local memory 1- is a memory that temporarily holds data when loading data on an extended storage device. The : of the work area where the sorting is to be performed. A mark register is a register bit that marks a logical delimitation (for example, a word boundary) of data loaded from extended storage.
Correspondingly, the corresponding bit in the mark register is 1'' if the segment is being accessed by a segment.
', and is a register that holds data that becomes "o" when it is not an access target (hereinafter, this data is referred to as a mark). FIG. 8 is a schematic block diagram of the paging processor 107's logic circuit for buffering read data and relocating the local space using the mark 1 register. When the logic circuit of FIG.
The number of data to be loaded from the extended storage device is set to 1 in the FF 800. At the same time, counters 801 and 802 are reset via path 851, and the starting address of the local memory+1 space to be loaded from the extended storage device is set in counter 802. The starting address of the counter 802 and the increment value on the FF 803 are added every clock, and the result is sent to the extended storage device 804 as an address via the 1 register 823 and the path 853. In order to simplify the drawing, FIG.
The activation and operation instruction signal paths to and associated logic have been omitted. −39= Counter 801 is synchronized with counter 802 and operates 1,
, the first value is taken from II II II by the incremental value FF821.
ing. The output of the counter 801 is compared every evening by the 7-comparison circuit 805 via the register 822, and when it matches the number of data to be loaded into the FF 800, the count up of the counters 801 and 802 is inhibited by the register 824, This inhibition, which is performed via path 852, is not released until a reset instruction is received from path 851. After the request and address are sent to the expanded storage device 804 via the path 853, an advance signal is sent from the expanded storage device 804 to the path 854 after several tens of timings, and then the read data is sent to the expanded storage device 804 via the path 855. Sent via intermediary. Here, the explanation will be simplified and the following assumptions will be made to clarify the basic part of the operation of the paging processor. 1°C Extended storage timing is four times the period of the paging processor. (2) The response data for the IJ request to the extended storage device is 111 times the processing data width of the paging processor. ('11 In Figure 8, the circuit operates at the timing of expansion memory installation. However, the part surrounded by dotted lines operates at the timing of the paging processor. The logic circuit 810 is a cycle counter that operates at the timing of the paging processor. The value is periodically taken as 0, 1, 2, 3, O, etc., and this value is sent to the path 856''2.It is controlled by the signal l2 of the selector 811 and the path R561-. , the data stored in +?FB+2 to 815 that has been D-coded from the extended storage device 804 is sequentially sent to the path 857''2.Meanwhile, the mark data is sent to the path 860. Sent via FF8
] 6 and then sent to the stack 817. In the stack 817, the extended memory "Ji"
The mark data is held until the data advance from 04 is received. In FIG. 8, only two stacks of stacks 817 are shown to simplify the drawing. After advance comes to path 851, cook data table F in stack 817
The mark data on aFF 818 transferred to F8 1 1'l is also transferred to FFl'l I 2. Similarly to the data of 8151, the mark data on aFF 818 is transferred to selector 819.
l:i! ltl'i! is performed, and path 8611m is sent. This mark data becomes an input to the logic circuit 1'120, and if the mark is 1'', the signal on the path 857-t: is sent to the path 862-): without processing.
(I II By setting the data on the path 862 to "0" regardless of the input data so far, preparations for relocation of the subset of the local memory i1 space have been completed. 9th In order to write the data on path 862 in FIG. 8 to the main memory, the figure performs processing to rearrange the order of some data so that m-separate accesses are partially continuous, and This is a schematic block diagram of a logic circuit that generates At1NOS as the writing destination of the device. The data on path 862 is once latched into FF900. At the next timing, it is determined whether the data in FF900 is PA0''''. A check is made in the comparison circuit 901.FF
When the data on 900 is not 170 II, puff! 1
``, s 0.1- is sent a bar 11 node signal. Child-9 is `` n '' low pass! !I n 'l, RAIV (readout port 904, main memory i3 porter 905 management circuit τ that controls the operation and stop 8 temporary management circuit 1) 02 path 9
The signal of 52 h can be used for one pointer including one pointer. (
Pass 951 (1 pass! It is the east line of 152,953,954.) At the second time, pass 950 to Balifu 1; Shinsodo pass 95':! The enable signal of 1 is generated in the A N D circuit 906, and the logical product is t'I. is FF91
Count up based on the updated value of 7 and store it in RAM910.
゜911's writing a1~lnos is a cow T friend. RAM91
0. qll (shi[1-cal memory, used as follows: 1
゛、Komaro.・1-1

[゛MeR/1.19] What happens to n or the writing target? (2) When it becomes impossible to write to the RAM, the management circuit 9
It acts on the switching circuit 912 to use 4911 for writing to 02 RA, and connects the data path. tl) When the writing destination is switched by writing J-■, RAM 9 to which data has already been written is set to 0, RA becomes M, and 5 successive outputs become possible.
Tapas connections are made in switching circuit 912. (2) When it becomes impossible to write to R and AM911 to be written to, the same RAM switching as in item number Q) occurs. 1) In repeating ~■, FF818 in Figure 8
If "0" exists in the mark data, the write pointer 9
Updating the value of 03 is slower than updating the value of read pointer 904, but since the banks of the write/read RAM are different, there is no need to compare the two pointers. When writing to RAM,
The data to be written is FF until write valid is generated.
913. - Reading from RAMs 910 and 911 is performed as follows. When the read pointer 904 is activated by the management circuit 902 via the path 952, the pointer is set to FF at every timing of paging=44-g/'rl seso.
It is updated with a value of 918. The output value of this pointer 904 is used to directly read RAM'910.911.
゛+ itzu, RAM9] O,! RAM in which the table for generating At1nos for reading 111 is stored
It is used as an atnos to cite 914. The 1 novel conversion circuit for each signal to access the 1 year old RAM 914 in 22 is all omitted, the 2 RA
For the bow I of M914, go up R, AM910 nu 91] 1] int, ], 2, 3° 4.5... As in the order of expansion storage device 804 in Fig. 8), The read data is 1.3', 2. /l, 5, etc. You can partially change the order and request it. This operation makes it possible to a) convert the local memory space into the optimal FT city for sagmen 1 to 2 without making the structure of the real memory space of extended storage device-1 match the structure of the local memory space; Become. The values in the conversion table in RAM 9141- must be initialized and turned on through path 955 before the logic circuit shown in the rectangular diagram is activated. The data read in this way is processed by a switching circuit 916 by a logic circuit 915 that manages the main storage device to which the data is written.
An instruction is then given to select the appropriate path 960 and 961. Here, paths 960 and 961 are the main storage device 10.
4,105 (see Figure 1). R
If the value in the AM successive pointer 904 exceeds the memory range of the RAM 914, a report thereof is sent to the management circuit 902 via a path 968. The main memory address is generated as follows. Main memory write pointer 905 is initialized via main memory write start address data 96G when the logic circuit of FIG. 9 is activated. In synchronization with the timing when the RAM successive pointer 904 is activated by the management circuit 902, the main memory write pointer 9
05 is counted up according to the value of FF9+9. The generated write address is. Register 922. are sent to the switching circuit 916 via the path 967, and are sent to the corresponding main memory device 104.
Or sent via 962.963 to 105. Pointer 904 and 905 management circuit! Figure 10 shows the logic for the segments to access and store the memory space in main memory 10.1.105. This is a general block diagram. The data of path 8571- in FIG.
It is latched to n11. 10, the logic circuit 1002 is 'R, A N, y write pointer +003°R
AM read read pointer 1004 main memory write pointer 10
This is a management circuit that controls starting and stopping of 05. In the initial state, all pointers can be counted up.
What's the condition? When data is stored in the FF 1000 from cell number 1 to cell number 1, a valid signal is sent to the path 9804 for counting up the writing point. The AND circuit 1008 performs a logical product of the z<lid signal and the path IO521=, and inputs the result to the write counter 1003. At the same time, the management circuit 10
It acts on the switching circuit 100G so that data can be written to the 02 RAM I OI O or 1011, and connects the data path 1055 to the RAM to be written. FF10f')1 is placed to hold data for the processing described in Section 17-1. The usage of the two RAMs 10IO, If) 11 is the same as in the case of the local memory space where segment access is performed as described above. The RAM read pointer 1004 is activated by the management circuit 1002.
051 to generate a subsequent address for the RAM that has already been written. The subsequent address passes through the register 1056 and the switching circuit 1006 to access RAM 1.0IO or +011. The data read from RAM10IO or 1011 is transferred to the main memory +04 or 105 by a switch/knob circuit 1007.
60 or 1061. The main memory address at which data is written is generated by the write pointer 1005. The pointer is started by the management circuit 1002, but before starting counting up, it is necessary to set the starting address of the area on the main memory where data is to be stored via the path 1057. Main memory write pointer 1005 RAM if? , Depo, Inter 100
4. Sync and operate

[−・The generated main memory write at 1 nos is the register I n + 7. pass 1058
through the switching circuit 1007.
(10) Manages writing/reading 11- of storage device 10/l, 105;
The main storage device to be written to is selected by the management circuit 915 (FIG. 9), and the address data is sent out on the path 1062 and 1063. Next, the operation of storing the local memory space on the main memory of the paging processor into the expanded storage device will be explained using FIGS. 11 and 12. FIG. 11 is an approximate block diagram of a part that performs sorting of data in a subset of the local memory space when referenced to segment 1. In FIG. 11, main storage device 1
The data read from 04 or Ike+05 is sent to Soi+Zowa path 1 along with a valid signal indicating the validity of the data.
It passes through 152.1150 or 1153.1151 and becomes an input to the switching circuit 1102 and 1101. -jf, there is a logic circuit 1100 that manages the number of the main memory device currently being accessed by the paging brothenosa. The contents of the management circuit 1100 act on switching circuits 1101 and 1102 via a path 1154, thereby establishing a data bus connection with the main memory device being accessed by the paging processor. Through this combination, 5 valid signals pass]]55. J-, the data is sent out on path 1159. Logical time vfS] 104.1105 is
These are the RAM write pointer and read pointer. The Kowara pointer is set to pass 1 by the management circuit 1106.
156.1157. In the initial state, the pointer 1104 is in a count-up enabled state, that is, when the signal value of the path +157-1 is ``bit''.
l 554 2nd valid signal to Nn circuit 1103
The AND is done with #), and the RAM write pointer 1104 is set to F.
This operation counts up according to the value of FIIIG11 and synchronizes with the arrival of data from main memory7.
The R'AM write at Inos is generated. In FIG. 11, 1110 and 1111 indicate RAMs. The usage of these two 'RAMs is shown in Figure 9.
Same as n 10 and 911, management times FIR + 1
According to the path coupling instruction to the switching circuits 1112 and 1113 by 06, either R or AM+110 or 1111 is used for writing. The other is used for reading. When writing to the corresponding RAM is completed, the management circuit 1106 activates the read pointer 1105. The pointer +105 is counted up every clock according to the value of the FF 1117, or the output of this pointer is passed through the register 1120, and is the address for quoting the RAM]]14. RAM +, ] ]
/l and the result is the read target R
A F14, ie address 1110 or 1111. By the second indirect address generation, data can be rearranged within the local space within the storage capacity of the RAM. In this way, the result of rearranging the data is sent to the path 116 (ml-). On the other hand, every time the contents of the read pointer 1105 count up, a valid signal is sent to the path +1611-. Valid FF] Pass 11 after necessary delay processing is performed in I5
621. The above processing holds true for a subset that is accessed locally by a segment in the memory space. For a subset whose segments are not accessed, reading from the main memory is performed by a logic circuit such that the value of the read pointer 1105 directly becomes the read address of the RAMs 1110 and 1111. This part is the same as in FIG. 11 except for the RAM11/1 part, so it is omitted. In this way, the data and valid retrieved from the main memory are merged into a subset to which segment access is performed and a set to which segment access is not performed in the next logic circuit. At this time, when reading two subsets from the main memory, if they are read at the same pitch, if segment access is biased to one of the subsets, the read data with the slower pitch will be read out to the next stage logic circuit. This causes conflict within the body. For this reason, it is necessary to control successive access of local memory space from the main memory for normal operation of the next stage logic circuit. A path 1170 is provided for this purpose. Second pass I+70. ．． When a significant instruction, that is, a request to temporarily suspend successive reading from the main memory, comes to I-, the second instruction interrupts the operation of the read logic circuit of the main memory and acts on the pointer management circuit 1106. 1. Pass 11
58. ] 157. Write via 1156 to interrupt the operation of the successive pointer. FIG. 12 stores the readout signal and data signal generated by FIG. 11, matches the timing differences between the paging processor and the expansion storage device, and uses the Mark 1 register to segment the data: FIG. 7 is a schematic block diagram of a logic circuit that performs the inverse operation of rearranging a subset of a local memory space depending on the presence or absence of a No. 1-7 access. According to FIG. 12, valid calls on path 162 are input to stack management circuit 1200. The stack management circuit 1200 controls the data stack 120
Data migration within 2 is managed by the arrival of a valid signal. Here, it is assumed that the stack management circuit 1200 and the stack 1202 are related to reading a portion of a subset of the local memory space in which segment 1 is accessed. Similarly, the stack management circuit 1201 and the stack 120
3 relates to reading of a portion where segment access is not performed. In FIG. 12, mark data is once latched in stack 1204 via path 1250 and later stored in mark register 1205. The cyclic counter 1206 uses this mark register 1.
205 are sequentially quoted, and it is determined whether data from the stack 1202 or 1203 should be quoted. This quotation information is transmitted to the stack management circuits 1200 and 1201 and the switching circuit 1207 via a path 1251. and the pitch of the data going into the stacks 1202, 1203. Since the quote pitches are not synchronized, it is possible for the stack to become full. At this time, the management circuit +200.1
．． 201 instructs the logic circuit that is sending data via path 1170 or 1252 to interrupt the sending. Data selected by switching circuit 1207 is stored in stack 1209. A circuit that manages data migration within the stack 1209 is a second stack management circuit 1208. This management circuit 1208 receives the paths +253, -.
When the data migration of Statuino + 209-hi is managed by the valid signal of 1-, four valid data are received, and the stack 1209 is filled with all the data in the tack. is transferred to the 1-no register 1210 at the same time. The reason for managing this validity comes from the fact that the timing of the basing processor is 1/4 synchronous with that of the expanded storage device. - Path from switch 9 circuit 1207 to path 12531-
The signal outputted to Barin 1 is reduced to 1/4 valid by the cycle force 1 nonta 1211, and is passed to IE, +254, . Be sent to 11. This path I25
/1.1- data is stored in the register 1210 of the register 1210 in synchronization with the signal 1210. Therefore, the output of the 1-no register 1210 can be sent as data to the extended storage device. Next, we will discuss the relationship between subset relocation and segment access in the local memory space used in the explanation of the paging processor described above, mark data given as data to logic circuits, and RAM for rearranging the order of data.
(For example, the RAM 914 in FIG. 9) will be described using two pieces of initial information. These pieces of information relate to the software operated on the vector processing device of the present invention, and will be explained here because they are closely related to the logic circuit operations shown in FIGS. 8 to 12. Immediately after the program is segmented, the local memory space has a configuration as shown in FIG. 13a. In FIG. 13a, each subset A, B, and C are the data of a statement that is accessed consecutively, the data of a statement that is accessed two times non-successively, and the data of a statement that is accessed consecutively and two
A subset of statements that performs both jump and jump accesses. The following operations are performed to optimally configure this local memory space. (2) The subset is transferred directly from the expanded storage to the main storage. In the QI quantity focus B, parts necessary for data processing in the segment and parts not necessary exist alternately. Therefore, 1,0,1. O...over O, I, n
,] ...Prepare the mark data of the inner pattern as shown in B1 set where segment access is performed on O + LF and Re units, and 7 accesses are performed t'L Pa:I B7
The set and the two that are separated into the two are created. Regarding the differences among the item numbers, the same process may be used to manage other data, such as the starting address for reading or writing on the extended storage device or the main storage device, with only this mark data. At this time, B, set, is placed immediately after B, offshore. This rearrangement of the subset turns two non-consecutive accesses into continuous accesses. tetl kebu [means modification of one gram itself. Even in such a case, the vector processing device of the present invention allows vector processing to be performed by modifying the protonorum itself, as described above. tg+ Subset C is a feature of Beta 1~R processing,
Taking advantage of the fact that the result does not change even if the order of operations is swapped, we can combine the data that is the remainder of 2 or O with the data that is 1 and set it as I.
-The main memory structure is as follows: fJ'. The second set is denoted by C'. For example, +7] Gerodo I, 3,
2, 4.5, 7, 6, 8 degrees, etc., to a subset of the main memory 1-Jl. Due to this address -5, two discontinuous 7' noses are not always discontinuous, but are partially continuous. For a main memory device with a configuration of Is it necessary to modify 7'?
,stomach. 1. To generate a local memory space with the black address shown in the table, add l, 3 to the RAM 911 in Figure 9.
, 2, 4. All you have to do is set the data (address) like... An overview of the local memory space reconstructed as described above is shown in FIG. For the mark data and data order change data, send them to Seno 1.Insert the instructions to the controller 1 and install it in the roll processor. Next, ``1-Rubrosessor and Beta 1-Ru-''
Access to main memory of j11 setter [1 case]
ni-) r explanation 9 local ゛ Reconstruction of memory space tN row h f+'l ket 41; -Coldness 1, each processor': + (hlj p) By adding a constant to 1.1 nof, we can find the at1 nos of the 1f storage device 101-1. The local 'memory space has been reorganized! 11. Figure 13 1) The boundary of the subset 4 has been changed/I.
'L, tl, if you want to re-create the local memory space, you can use the same relocation processing. It is possible to process large-scale professional notebooks and notebooks that require 11 memo spaces of the same size as the device capacity.Extended memory (opens the eyes)
It is possible to use 1 + 9 memory devices, which are also slow to use, and is more economical than implementing a 7-torque processing device. The reduction in data transfer speed due to the use of memory elements with slow cycle times in the expanded storage device increases the processing speed of the paging processor, which increases the processing speed of the expanded storage device and data transfer. By increasing 11 and increasing the number of interleaves, this decrease in data transfer speed can be compensated for.The economic disadvantage of having multiple main storage devices is as follows:
As expected from current scientific computing practices, this can be ignored. That is, when solving a two-dimensional or three-dimensional differential equation, when discretizing the equation using the finite element method, nodes of the order of 104 are often taken. At this time, if the data lJ is 4 to 8B, and the working array is 7, it will be 160Kr3.
One Do process can be performed in the order memory. One segment is treated as several DO processes. Even assuming that there is no array commonly used between arrays, one main storage device of 2 MB or less is sufficient. On the other hand, since an expanded storage device is on the order of several hundred MB, its capacity is on the order of 10-2 times that of the main storage device and the expanded storage device. Therefore, the economic loss of implementing multiple main memories in a vector processing device can be ignored. In the Beta 1 Health processing device of the present invention, the Control 1 Roll [
It is possible to fix various instructions for operating 1 processor, 1 processor, and 9' processor in parallel, and the instructions are controlled by hardware.
The loss time for operating three processors in Mi rows is minimized.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of the vector processing device according to the present invention, FIG. 2 is a schematic block diagram of the block diagram, FIG.
The figure is a diagram of the operation of both the basing and control processors, Figure 5 is a conceptual diagram of the optimal 11'' vector processing program, and Figure 6 is the lever 1- 1 circuit block diagram, Figure 7 is a block diagram of the second stage lever = 1 circuit of the control processor,
Figure 8 shows the rl-1 (1 (noh)
The r1 block diagram, Figures 9 and 10 show the editing function block "1)" for the local memory space of the page loader.
Figure 11 is a block diagram of the first stage logic of the store operation of the pacing block ``1-9 Figure 1. , FIG. 13 is a conceptual diagram of the local memory space.
-Rup "I Sera, 102 Beg J.Rup" 1 Setsa, +03.106 Slnoting Circuit, +
04,105 Main storage. 107 Begeso'J processor, 108.1 Widespread storage device 109 Main storage device.゛・'1Figure 21)

Claims (2)

[Claims] (1) A plurality of main storage devices, an expanded storage device of the main storage device, and three types of processors: a paging processor, a vector processor, and a control processor, and the control processor is provided with data processing of the three types of processors. In order to execute the above in parallel, an instruction stack for separately holding instructions for the three types of processors and a decoding process management mechanism for time-sharing decoding of multiple instructions on the instruction stack are provided, and the paging process is performed in parallel. Loading an area on the extended storage device used by a subset of the program into a specified main storage device in order to cause the processor to execute the program existing on the expanded storage device on the plurality of main storage devices. - A vector processing device, characterized in that it is provided with a logic mechanism for storing and a logic mechanism for editing the arrangement of data in a designated area, and the vector processor processes vector instructions on a main storage device under the control of the control processor. . (2) The vector according to claim 1, wherein the expanded storage device has a larger capacity and lower speed than the plurality of main storage devices, and is used to store a large-scale program. Processing equipment.