JPS6180591A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To execute a high speed reading in the two-way direction by outputting serially the output signal of a sense amplifier in a dynamic type RAM in accordance with the shifting action of a two-way shift register. CONSTITUTION:When address signals A0-A8 are supplied at a low level together with a chip selecting signal inversion CS and a refreshing control signal inversion RESH, a memory condition of the memory cell connected to the word line designated by this result is amplified by a sense amplifier SA. A static type memory cell SRAM receives an amplifier output in parallel. Since a shift lock phirs is supplied to a shift register SR, SR successively shifts a logical '1' signal set in accordance with the shift direction. Since the memory cell SRAM is successively selected in accordance with the shifting action, the reading signal is serially sent through a main amplifier MA and a data output buffer DOB. The shift direction of the shift register SR is set in the down to up/up to down directions in the figure by the low level/high level of a write enable signal inversion WE.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective for use in dynamic RAM (random access memory).

[Background technology]

When printing characters or the like using a printer, if the printing operation by the printer head is performed in both directions, the printing speed can be increased because unnecessary changeover operations are unnecessary. In this case, a control circuit (such as a microprocessor) is required to switch the reading direction of the dynamic RAM in which character codes and the like are written in accordance with the printing direction of the printer head.

Therefore, the inventors of the present application have developed a semiconductor memory circuit that can selectively change the reading order of data, such as the data supplied to the printer as described above, with a simple configuration.

[Object of the Invention] An object of the invention is to provide a semiconductor memory device that can perform bidirectional high-speed read operations.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the output signal of the sense amplifier in the dynamic RAM is serially output according to the shift operation of the bidirectional shift register.

(Embodiment) FIG. 1 shows a block diagram of an embodiment of the present invention.

In the same figure, each circuit block surrounded by a dotted line is formed on a single semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing techniques, but is not particularly limited. D7. AO~Al
4. WE, C3, RESH and V cc, V
ss is its external terminal, and power is supplied to the terminals Vcc and Vss from an appropriate external power supply device (not shown).

The circuit symbol M-ARY is a memory array, which includes a storage capacitor and an address selection MOS F.
Known 1MO3 type memory cells made up of ET are arranged in a matrix.

In this embodiment, although not particularly limited, the memory cells include a pair of complementary data lines arranged in parallel.

2 whose input/output nodes are connected to either one of D
Arranged in an intersection manner.

The circuit symbol PC indicates a data line precharge circuit. The precharging operation of the memory array of this embodiment is not particularly limited, but is performed using a pair of complementary data lines (
The same applies to the common complementary data line described later).
By simply short-circuiting with T, an intermediate level of approximately Vcc/2 is obtained. This allows from 0 volts to VC
Compared to those that charge up to the C level, the amount of level change is small, and even if the gate voltage of the precharge MO3FET is used at a normal logic level (Vcc), it can be turned on in a sufficiently unsaturated state, so it is possible to perform precharge operation. can be performed at high speed and with low power consumption.

Then, as mentioned above, set the precharge level to approximately Vcc.
/2, so even when reading the memory cell, the memory cell switch MOS
Even if a normal logic level (Vcc) is used as the gate voltage (word line selection voltage) of the FET, it can be turned on in a sufficiently non-saturated state, so the total charge of the information storage capacitor can be reduced without using a bootstrap voltage. Reading becomes possible. Furthermore, by using the precharge level of one data line on which no memory cell is selected as the read reference voltage, a dummy cell that forms the read reference voltage is not required.

What is indicated by the circuit symbol SA is a sense amplifier, which includes, but is not particularly limited to, a pair of power switches MO5FET each consisting of a P-channel inter-channel O5FET and an N-channel MO5FET for the power supply voltage Vcc and the circuit ground potential Vss. CMO3 (complementary MO3) with
It is composed of a launch circuit, and its pair of input/output nodes are coupled to the complementary data line D. The timing pulse φpa is for controlling the power switch MO3FET. In addition, N channel MO3FE
A non-inverted timing pulse φpa and an inverted timing pulse φpa are used to control the power switch MO3FET composed of T and P channel MO3FETs, but only the non-inverted timing pulse φpa is shown in the figure. The above pair of power switches MOS F
ET is turned off immediately before precharging. This creates a complementary data line, D is in a floating state, and V c
c, maintain V ss level.

Denoted by circuit symbol C-5W is a column switch that couples a selected complementary data line to a common complementary data line in accordance with a column selection signal.

The circuit symbol R-ADB is a row address buffer, which receives external address signals from external terminals AO to A8 and outputs internal complementary address signals aO to a8 . a
Process and form O to a8.

In the following description and drawings, a pair of internal complementary address signals, for example 301-0, will be referred to as internal complementary address signal 10.
I will express it as Therefore, the upper' orientation portion complementary address signals aO to a8 . aO-18 is represented as internal complementary address signal aO-18.

The circuit symbol C-ADB is a column address buffer, which receives external address signals from external terminals A9 to A14 and outputs internal complementary address signals a9 to a1.
4. Form a9-d14. In addition, in accordance with the way of representing the internal complementary address signals described above, in the drawings and the following description, the internal complementary address signals a9 to a14 . a9～a
14 is represented as internal complementary address signals 19 to a14.

The circuit symbol R-DCR is a row address decoder, which receives internal complementary address signals 10 to 8 via a multiplexer MPX, which will be described later, and outputs M-AR.
A Y word line selection signal is formed. This word line selection signal is synchronized with the word line selection timing signal φX.
-To be communicated to ARY.

The circuit symbol MA indicates a main amplifier, which has the same circuit configuration as the sense amplifier SA described above. Note that this main amplifier MA selectively amplifies the read signal from the memory array M-ARY and the read signal from the static type memory cell SRAM, as will be described later.

The circuit symbol DOB indicates a data output cover sofa, which sends read data from the main amplifier MA to the external terminal I10 in response to a timing pulse φrw. Note that during writing, the timing pulse φ
Due to the low level of r-, this data output cover sofa DOB
is placed inactive (output high impedance).

What is indicated by the circuit symbol DIB is the data person cover sofa, and the timing pulse φrw connects the external terminal I.
The write data from 10 is transmitted to the common complementary data line.

Note that during reading, this DIB is rendered inoperable in the same manner as described above by the low level of the timing pulse φrw.

The various timing signals described above are formed by the following circuit blocks.

Although not particularly limited, the circuit symbol RATD is a 0 circuit symbol which is an address signal change detection circuit that receives address signals aO to a8 (or 1O-a8) and detects a change in the rise or fall of the address signals. Although not particularly limited, what is indicated by CATD is the address signal a.
This is an address signal change detection circuit that receives signals 9 to a14 (or a9 to a14) and detects a change in the rising or falling edge thereof.

The address signal change detection circuit RATD includes, but is not particularly limited to, an exclusive OR circuit that receives each of the address signals aO to a8 and their delayed signals, and an OR circuit that receives the output signals of these exclusive OR circuits. It is composed of That is, an exclusive circuit for receiving an address signal and a delayed signal of that address signal is provided for each address signal. In this case, nine exclusive OR circuits are provided, and the output signals of these nine exclusive OR circuits are input to the OR circuit. When one of the address signals aO-a8 changes, this address signal change detection circuit RATD forms an address signal change detection pulse φr synchronized with the change timing.

The address signal change detection circuit CATD has the same configuration as the address signal change detection circuit RATD. That is, it is comprised of exclusive OR circuits that receive address signals a9 to a14 and their delayed signals, respectively, and an OR circuit that receives output signals from these exclusive OR circuits. This address signal change detection circuit CA
Like the address signal change detection circuit RATD, when any of the address signals a9 to a14 changes, TD forms an address signal change detection pulse φC synchronized with the change timing.

The circuit symbol TG is a timing generation circuit, which forms the main timing signals etc. shown as the representative above. In other words, this timing generation circuit TO
receives address signal change detection pulses φr and φC, write enable signal WE and chip selection signal cs supplied from external terminals, and forms the above-mentioned series of timing pulses.

The circuit symbol MPX is a multiplexer, and the address buffer R-
The decoder R selectively outputs the internal complementary address signals aO to a8 formed by the ADB and the internal complementary address signals 10 to 18 formed by the automatic refresh circuit REF.
- Inform DCR.

The circuit symbol Vbb-G indicates a substrate bias voltage generation circuit. In this embodiment, although not particularly limited, an oscillation signal of an oscillation circuit included in this substrate bias circuit vbb-G is used to generate a shift register S to be described later.
A shift clock φsr of R is formed.

The circuit symbol REF is an automatic refresh signal, which includes a fresh address counter, a timer, etc., and the refresh signal RES from an external terminal.
It is activated by setting H to low level. That is, when the refresh signal RESH is set to a low level while the chip selection signal 3S is at a high level, the automatic refresh circuit REF switches the multiplexer MPX and transmits the internal address signal from the built-in refresh address counter to the row decoder R-DCR. A refresh operation (auto-refresh) is performed by selecting one word line. Also, if the refresh signal RESH is kept at a low level, a timer is activated and the refresh address counter is incremented at regular intervals, during which time the refresh address counter is continuously refreshed. Performs an action (self-refresh).

In this embodiment, the following circuits are added to serially read out the memory array M-ARY in the word line direction.

That is, the memory array M-ARY is provided with static memory cells SRAM that each receive and take the output signal of the sense amplifier SA.

Furthermore, a shift register SR is provided to selectively read out these memory cells SRAM.

This shift register SR is a bidirectional shift register whose shift direction can be switched by a combination of control signals to be described later.

The output signal of the memory cell SRAM selected by the shift register SR is supplied to the main amplifier MA and sent out serially.

Next, the bidirectional continuous read operation of this embodiment will be explained according to the timing diagram shown in FIG.

That is, the following operation mode is activated by the combination of the chip selection signal C3, the write enable signal WE, and the refresh signal RESH.

For example, the chip selection signal C5 and the refresh control signal R
Both ESH and address signal AO- are set to low level.
When A8 is supplied, the storage state of the memory cell connected to the word line designated by the address signals AO to A8 is amplified by the sense amplifier SA. The static memory cell SRAM receives the amplified output in parallel. After that, the shift clock φrs is supplied to the shift register SR, so that the shift register SR is set to logic "1" according to the shift direction.
Shift the signals sequentially. The static memory cells SRAM are sequentially selected according to this shift operation.
The read signal is serially sent out through the main amplifier MA and the data output sofa DOB. In addition,
Although not particularly limited, the shift direction of the shift register SR is set from bottom to top/top to bottom in the figure, depending on the low level/high level of the write enable signal WE.

Note that the chip selection signal C8 and the refresh signal RESH
When C8 is at a high level, the chip is in a non-selected state (standby state), and when the chip selection signal C8 is at a high level and the refresh signal RESH is at a low level, a refresh operation is activated. A distinction is made between the operating mode and the continuous read operation described above.

〔effect〕

(1) By serially transmitting the stored information of the memory cell selected by the word line selection according to the shift operation of the bidirectional shift register, the stored information in the word line direction can be selectively output serially from both directions. can get.

(2) Due to (1) above, when used as a memory for a printer, the readout direction can be easily specified according to the direction of the printer head without using a special address generation circuit (control circuit). can get.

(3) Since the information stored in all memory cells is taken out in parallel in the word line direction and sent out serially according to the shift operation of the shift register, the operation of selecting memory cells one by one can be omitted. This has the effect of enabling high-speed read operations.

(4) The read signal of the sense amplifier SA is temporarily transferred to the static type memory cell, and the static type memory cell is selected according to the shift operation of logic "1" of the shift register, and any bit of the shift register is transferred to the static type memory cell. By storing the logic "1", an effect can be obtained in that it can be serially transmitted from any bit among the plurality of bits.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without advancing the gist of the invention. Nor. For example, the shift clock of the shift register and the signal specifying its shift direction may be supplied from an external terminal, or the static memory cell SRAM may be omitted and the amplified signal of the sense amplifier SA may be directly supplied. It may be sent in parallel to a shift register and shifted.
Furthermore, the combination of external control signals for continuous readout as in the above embodiments can be implemented in various embodiments, or new control signals may be provided.

[Application field]

The above explanation will mainly focus on the dynamic type RA, which is the application field that is the background of the invention made by the present inventor.
Although the description has been made regarding M, the present invention is not limited to this, and the same operational functions as described above may be added to a static type RAM as well.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a timing diagram for explaining the operation of the embodiment circuit shown in FIG. 1 above. M-ARY...Memory array, PCI...Precharge circuit, SA...Sense amplifier, I? --A DB...Row address buffer, C-5W...Column switch, C
-ADB...Column address buffer, R-DCR...
Row address decoder, C-DCR... Column address decoder, MA... Main amplifier, RATD, CATD
・・Address signal change detection circuit, TO・・timing generation circuit, REF・・automatic refresh circuit, DOB・・・
Data output cover sofa, DIB... data manual buffer,
MPX: multiplexer, Vbb-G: substrate bias circuit, SR: shift register, SRAM: static type memory cell.

Claims (1)

Claims: 1. A semiconductor memory device characterized by having a function of serially outputting an output signal of a sense amplifier in a dynamic RAM according to a shift operation of a bidirectional shift register. 2. The circuit that serially sends out the output signal of the sense amplifier is composed of a static memory cell that receives the output signal of the sense amplifier, and a bidirectional shift register that forms a selection signal for this memory cell. A semiconductor memory device according to claim 1, characterized in that: 3. The serial read operation mode according to the shift operation of the bidirectional shift register is activated by a combination of a plurality of external control terminals. Semiconductor storage device.