JPS6179899U - - Google Patents
Info
- Publication number
- JPS6179899U JPS6179899U JP16507684U JP16507684U JPS6179899U JP S6179899 U JPS6179899 U JP S6179899U JP 16507684 U JP16507684 U JP 16507684U JP 16507684 U JP16507684 U JP 16507684U JP S6179899 U JPS6179899 U JP S6179899U
- Authority
- JP
- Japan
- Prior art keywords
- holding circuit
- memory device
- semiconductor memory
- circuit
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 230000014759 maintenance of location Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Power Sources (AREA)
- Static Random-Access Memory (AREA)
Description
図面はこの考案に係わる半導体記憶装置の記憶
保持回路の一実施例を示す回路図である。
１１…半導体記憶装置、１２…スイツチングダ
イオード、１４…電池。
The drawing is a circuit diagram showing an embodiment of a memory holding circuit of a semiconductor memory device according to the invention. 11...Semiconductor storage device, 12...Switching diode, 14...Battery.
Claims (1)
電池との間に順方向漏洩電流が多いＰＮ接合回路
を設け、この漏洩電流によつて前記半導体記憶装
置を記憶保持状態に保つ構成としたことを特徴と
する半導体記憶装置保持回路。 (2) 前記ＰＮ接合回路はスイツチングダイオー
ドからなることを特徴とする実用新案登録請求の
範囲第１項記載の半導体記憶装置の記憶保持回路
。 (3) 前記ＰＮ接合回路はダイオード接続された
トランジスタからなることを特徴とする実用新案
登録請求の範囲第１項記載の半導体記憶装置の記
憶保持回路。[Claims for Utility Model Registration] (1) A PN junction circuit with a large forward leakage current is provided between a semiconductor memory device and a backup battery for memory retention, and this leakage current causes the semiconductor memory device to enter a memory retention state. 1. A semiconductor memory device holding circuit, characterized in that the semiconductor storage device holding circuit is configured such that the holding circuit maintains the holding circuit. (2) A memory holding circuit for a semiconductor memory device according to claim 1, wherein the PN junction circuit comprises a switching diode. (3) A memory holding circuit for a semiconductor memory device according to claim 1, wherein the PN junction circuit is composed of a diode-connected transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16507684U JPS6179899U (en) | 1984-10-31 | 1984-10-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16507684U JPS6179899U (en) | 1984-10-31 | 1984-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6179899U true JPS6179899U (en) | 1986-05-28 |
Family
ID=30722939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16507684U Pending JPS6179899U (en) | 1984-10-31 | 1984-10-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6179899U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5819614U (en) * | 1981-07-29 | 1983-02-07 | セイコーエプソン株式会社 | Spring bar structure for watches |
-
1984
- 1984-10-31 JP JP16507684U patent/JPS6179899U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5819614U (en) * | 1981-07-29 | 1983-02-07 | セイコーエプソン株式会社 | Spring bar structure for watches |
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