JPS617960A - バツフア無効化制御方式 - Google Patents

バツフア無効化制御方式

Info

Publication number
JPS617960A
JPS617960A JP59128621A JP12862184A JPS617960A JP S617960 A JPS617960 A JP S617960A JP 59128621 A JP59128621 A JP 59128621A JP 12862184 A JP12862184 A JP 12862184A JP S617960 A JPS617960 A JP S617960A
Authority
JP
Japan
Prior art keywords
register
main memory
tag
tag2
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59128621A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0148571B2 (en:Method
Inventor
Miyuki Ishida
幸 石田
Takashi Chiba
隆 千葉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59128621A priority Critical patent/JPS617960A/ja
Priority to CA000484187A priority patent/CA1241768A/en
Priority to US06/746,536 priority patent/US4760546A/en
Priority to EP85304443A priority patent/EP0165823B1/en
Priority to ES544431A priority patent/ES8609771A1/es
Priority to AU43934/85A priority patent/AU552199B2/en
Priority to DE8585304443T priority patent/DE3584476D1/de
Priority to KR1019850004453A priority patent/KR910001735B1/ko
Priority to BR8503021A priority patent/BR8503021A/pt
Publication of JPS617960A publication Critical patent/JPS617960A/ja
Publication of JPH0148571B2 publication Critical patent/JPH0148571B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP59128621A 1984-06-22 1984-06-22 バツフア無効化制御方式 Granted JPS617960A (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP59128621A JPS617960A (ja) 1984-06-22 1984-06-22 バツフア無効化制御方式
CA000484187A CA1241768A (en) 1984-06-22 1985-06-17 Tag control circuit for buffer storage
US06/746,536 US4760546A (en) 1984-06-22 1985-06-19 Tag control circuit for increasing throughput of main storage access
EP85304443A EP0165823B1 (en) 1984-06-22 1985-06-21 Tag control circuit for buffer storage
ES544431A ES8609771A1 (es) 1984-06-22 1985-06-21 Un circuito de control de etiquetas en un aparato de controlde acceso a memoria
AU43934/85A AU552199B2 (en) 1984-06-22 1985-06-21 Tag control circuit for buffer control
DE8585304443T DE3584476D1 (de) 1984-06-22 1985-06-21 Etikettensteuerungsschaltung fuer pufferspeicher.
KR1019850004453A KR910001735B1 (ko) 1984-06-22 1985-06-22 버퍼기억장치용 태그 제어회로
BR8503021A BR8503021A (pt) 1984-06-22 1985-06-24 Circuito de controle de sinalizador em um aparelho de controle de acesso de memoria em um sistema computador digital

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59128621A JPS617960A (ja) 1984-06-22 1984-06-22 バツフア無効化制御方式

Publications (2)

Publication Number Publication Date
JPS617960A true JPS617960A (ja) 1986-01-14
JPH0148571B2 JPH0148571B2 (en:Method) 1989-10-19

Family

ID=14989317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59128621A Granted JPS617960A (ja) 1984-06-22 1984-06-22 バツフア無効化制御方式

Country Status (1)

Country Link
JP (1) JPS617960A (en:Method)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0272453A (ja) * 1988-06-27 1990-03-12 Digital Equip Corp <Dec> 共有メモリ及び私用キャッシュメモリを有するマルチプロセッサコンピュータシステム
WO2007099614A1 (ja) * 2006-02-28 2007-09-07 Fujitsu Limited システムコントローラおよびキャッシュ制御方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0272453A (ja) * 1988-06-27 1990-03-12 Digital Equip Corp <Dec> 共有メモリ及び私用キャッシュメモリを有するマルチプロセッサコンピュータシステム
WO2007099614A1 (ja) * 2006-02-28 2007-09-07 Fujitsu Limited システムコントローラおよびキャッシュ制御方法
JPWO2007099614A1 (ja) * 2006-02-28 2009-07-16 富士通株式会社 システムコントローラおよびキャッシュ制御方法
US7979644B2 (en) 2006-02-28 2011-07-12 Fujitsu Limited System controller and cache control method

Also Published As

Publication number Publication date
JPH0148571B2 (en:Method) 1989-10-19

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