JPS6179240A - Semiconductor device - Google Patents

Abstract

PURPOSE:To effect a probe test in a short time easily by arranging a member for wiring shortage and a wiring for shortage previously on a mother chip. CONSTITUTION:A material for wiring shortage for probe test 5 and a wiring 6 are arranged on a mother chip 2 thereby shortening the all wirings 4. The member 5 is formed with a little smaller area than that of a semiconductor chip 3. Nextly a terminal 7 of a measuring device is brought in contact with wiring terminals P1 - P2, P2 - P3, P1 - P3... to effect the energizing test of those. After the energizing of those is confirmed, the part designated by a dot and dash line A, i.e., a part of the wiring 6 is removed to prevent the energizing among the wirings. By thus arranging the member 5 and the wiring 6 previously on the chip 2, the probe test can be made in a short time easily.

Description

Detailed Description of the Invention (rTechnical Field) The present invention relates to a semiconductor device, and particularly relates to a technique that is effective when applied to a probe device 1-technical means in a multi-chip semiconductor device mounted with a plurality of semiconductor chips. [Background Art] A multi-chip semiconductor device mounts a large number of semiconductor chips on a silicon wiring board (hereinafter referred to as a mother chip) by face-down bonding using a free-knob chip method. Therefore, the number of electrodes is, for example, 100 to 3.
There are as many as 00 pieces.

As the number of electrodes increases, the number of wires provided on the mother chip also increases, making it extremely difficult to perform a probe test to test for disconnections in the wires.

A silicon-on-silicon type multi-chip semiconductor device using a single-layer structure, that is, a multi-chip semiconductor device using a mother chip, is published by Nikkei McGraw-Hill [Nikkei Electronics J, June 11, 1984 issue] , no. 2, P136.

[Purpose of the invention]

An object of the present invention is to provide a technique that allows easy probe testing of wiring provided on a mother chip 42.

Another object of the present invention is to provide a technique that can improve the efficiency of probe testing of wiring provided on a mother chip in a multi-chip semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows.

In other words, by arranging a wiring shorting member and shorting wiring that are slightly smaller than the semiconductor chip on the mother chip on which the semiconductor chip is mounted, and separating the shorting wiring from the wiring after the probe test, This makes it possible to easily perform a probe test on the wiring provided on the mother chip L, and to improve the work efficiency.

Hereinafter, the configuration of the present invention will be explained along with examples.

In addition, in all the episodes, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

〔Example〕

1 to 3 are diagrams for explaining a semiconductor device according to an embodiment of the present invention, and FIG. 1 is a perspective view showing the overall schematic configuration of the semiconductor device with lead pins and wiring omitted; FIG. 2 is a plan view showing the wiring pattern provided on the mother chip L of the semiconductor device, and FIG. 3 shows the wiring pattern shown in FIG. FIG.

In FIG. 1, 1 is a package substrate, 2 is a mother chip with wiring, and 3 is a semiconductor chip.

In FIGS. 2 and 3, 4 is a wiring provided on the mother chip (3-2), which consists of a signal line, a power supply line, a ground line, etc. ), copper (Cu), or other metal wires.

P, to P8 and Q, to Q12 are wiring terminals (pads)
, 5 is a wiring shorting member provided on the mother chip 2, and has an area slightly smaller than that of the semiconductor chip 3. The wiring shorting member 5 is made of a metal thin film such as aluminum (AQ) or copper (Cu). The wiring short-circuiting member 5 may have any shape as long as it is short-circuited, such as a square, two circles, or a ring.

(i is a short-circuit wiring, for example, a metal wire such as an aluminum wire or a copper wire is used. 7 is a terminal of the measuring instrument.

First, as shown in FIG. 3, a wiring short-circuiting member 5 for the probe terminal 1 and wiring 6 are provided on the mother chip 2'' to short-circuit all the wiring 4. Next, the wiring terminal P I
P2, P2 P3, P+ Ps...81
Test 1 for continuity by applying the terminal 7 of the meter.

After these conductions are confirmed, the portion surrounded by the dashed line A, that is, a portion of the short-circuit wiring 6 is removed by etching or the like to make the wirings non-conductive. After that, wiring terminal PI P2. P2 P3, P+
Apply terminal 7 of the measuring device to Pa... and confirm that there is no continuity between them.

By providing the wiring shorting member 5 and the shorting wiring 6 on the mother chip 2 in advance as described above, the probe tests 1 to 1 can be easily performed in a short time, thereby improving the work efficiency. be able to.

In addition, in the process of forming the wiring shorting member 5 and the shorting wiring 6, the wiring 4 and the wiring 4 are made of the same metal.
Since it can be formed at the same time as forming the , the number of manufacturing steps is not increased.

〔effect〕

As explained above, according to the new technology disclosed in this application, the following effects can be obtained.

(1) By arranging a wiring shorting member and shorting wiring slightly smaller than the semiconductor chip on the mother chip on which the semiconductor chip is mounted, and arranging the shorting wiring and the wiring after the probe test. , it is possible to easily connect the wiring provided on the mother chip 1- to the terminal L1-butes 1 in a short time.

(2) By using the above (]), the work efficiency of Blobutes 1- can be increased to 1-. I can do it.

The present invention has been specifically explained above using examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and that various modifications can be made without departing from the spirit thereof.

For example, it goes without saying that the shape of the pattern of the probe test wiring can be varied as necessary.

In the embodiments described above, the mother chip was used as a wiring board, but it goes without saying that the present invention can be applied to other boards as well.

.

[Brief explanation of the drawing]

1 to 3 are diagrams for explaining a semiconductor device according to an embodiment of the present invention, and FIG. 1 is a perspective view showing the overall schematic configuration of the semiconductor device with lead pins and wiring omitted; Fig. 2 is a plan view showing the wiring pattern provided on the mother chip of the semiconductor device, and Fig. 3 shows the wiring pattern shown in Fig. 1 short-circuited with a short-circuit member and a short-circuit wiring. FIG. In the figure, ■...Package board, 2. Mother chip, 3
. . . Semiconductor chip, 4. Wiring, 5. Member for wiring short circuit, 6. Short circuit wiring, 7. Terminal of measuring instrument, P+ to Pa, Q+ to Q10. Wiring terminal (pad). Figure 2

Claims (4)

[Claims] 1. A semiconductor device characterized by having a structure in which a wiring shorting member and shorting wiring slightly smaller than the semiconductor chip are arranged on a wiring board on which a semiconductor chip is mounted, and the shorting wiring and the wiring are separated after a probe test. 2. 2. The semiconductor device according to claim 1, wherein a semiconductor wiring board is used as the wiring board. 3. 3. The semiconductor device according to claim 1, wherein the semiconductor device has a structure in which the probe test wiring and the wiring can be formed at the same time. 4. 3. The semiconductor device according to claim 1, wherein a plurality of semiconductor chips are mounted on the substrate.