JPS6178244A - Remote supervisory controlling method - Google Patents

Remote supervisory controlling method

Info

Publication number
JPS6178244A
JPS6178244A JP59199604A JP19960484A JPS6178244A JP S6178244 A JPS6178244 A JP S6178244A JP 59199604 A JP59199604 A JP 59199604A JP 19960484 A JP19960484 A JP 19960484A JP S6178244 A JPS6178244 A JP S6178244A
Authority
JP
Japan
Prior art keywords
signal
control
master station
selection
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59199604A
Other languages
Japanese (ja)
Inventor
Yasuhiro Noguchi
野口 康弘
Takao Nouchi
隆夫 野内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59199604A priority Critical patent/JPS6178244A/en
Publication of JPS6178244A publication Critical patent/JPS6178244A/en
Pending legal-status Critical Current

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  • Selective Calling Equipment (AREA)

Abstract

PURPOSE:To attain quick transmission between a master station and a slave station by providing a buffer memory for plural control information to a reception circuit of a slave station and receiving the next control signal from a master station even during the control of a device. CONSTITUTION:A device selection signal from the master station is inputted to a transmission/reception circuit 6 of a slave station 3 via a signal transmitter 2. A program of a ROM memory 9 is started by a microprocessor 7 in the slave station 3, and after it is confirmed that no device under present control exists, a signal received via an external bus 11 is outputted to the corresponding control signal output circuit 5-i. A selection relay of the corresponding CE12 is turned on and a selection end signal is returned to a data transmission/ reception section 4 through an external bus 11. When the microprocessor 7 receives a selection end signal from the control signal output circuit, a selection response signal is transmitted to the master station via the signal transmitter 2 through the transmission/reception circuit 6.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明はポーリング方式の情報伝送方法に係り、特に、
多重選択、及び、誤制御が許されないシステムにおいて
、連続的な制御を必要とされる機器の制御を行なう際に
迅速な制御と迅速な親局とのデータ伝送を必要とする情
報伝送装置の遠方監視制御方法に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a polling-based information transmission method, and in particular,
In a system where multiple selection and erroneous control are not allowed, remote information transmission equipment that requires quick control and quick data transmission with the master station when controlling equipment that requires continuous control. Related to supervisory control method.

【発明の背景〕[Background of the invention]

本装置が用いられるシステム構成図を第6図に又1本装
置の伝送タイムチャート及び制御信号出力タイムチャー
トを第7図に示す。親局1から子局3−nに対し機器選
択信号を送信し、機器選択信号を受けた子局3−nは該
当するCEの機器選択リレーをONにし、親局1に対し
機器選択応答信号を返す。親局1は子局3−nからの機
器選択応答信号を受けると選択された機器が正しいこと
を確認した上で、続いて子局3−nに制御信号を送信す
る。子局3−nは親局1からの制御信号を受信すると該
当する制御リレーをONL、親局1に対し制御応答信号
を返す。親局1は制御応答信号を子局3−nから受けと
ることにより一連の動作が終了し、次の動作に移行して
いく。
A system configuration diagram in which this device is used is shown in FIG. 6, and a transmission time chart and a control signal output time chart of this device are shown in FIG. 7. The master station 1 transmits a device selection signal to the slave station 3-n, and the slave station 3-n, which receives the device selection signal, turns on the device selection relay of the corresponding CE and sends a device selection response signal to the master station 1. return it. Upon receiving the device selection response signal from the slave station 3-n, the master station 1 confirms that the selected device is correct, and subsequently transmits a control signal to the slave station 3-n. When the slave station 3-n receives the control signal from the master station 1, it turns on the corresponding control relay and returns a control response signal to the master station 1. The master station 1 completes a series of operations by receiving the control response signal from the slave station 3-n, and moves on to the next operation.

ここで親局1はこの動作終了後、他の子局に伝送制御を
移行せず、連続して制御詮行なう場合(表示信号の集取
をも含めて)、先の制御が終了するまで、子局3−nは
親局〕からの信号を受は付けず、多数の機器を連続して
制御を行なう場合には、多大な時間を要し、他の機能が
マヒするという欠点があった。
After completing this operation, the master station 1 does not transfer transmission control to other slave stations, but if it performs continuous control (including collection of display signals), it will The slave station 3-n does not receive signals from the master station, and has the disadvantage that it takes a lot of time to control a large number of devices in succession, and other functions become paralyzed. .

尚、この種の装置として関連するものには特開昭58−
211248号公報があげられる。
In addition, related devices of this type include Japanese Patent Application Laid-Open No. 1986-
No. 211248 is mentioned.

〔発明の目的〕[Purpose of the invention]

本発明の目的はポーリング方式の情報伝送装置において
、同一子局で連続した制御を必要とする際に、迅速な制
御を行ない、伝送時間を大幅に短縮することによりシス
テム全体の機能が向上する情報伝送方法を提供すること
にある。
An object of the present invention is to provide information that improves the functionality of the entire system by performing quick control and significantly shortening the transmission time when continuous control is required in the same slave station in a polling type information transmission device. The purpose is to provide a transmission method.

〔発明の概要〕[Summary of the invention]

本発明はポーリング方式の情報伝送装置において、親局
からの子局に対する選択信号の伝送は単独的に行なわれ
ており、又、制御リレーの動作時間は大力の装置におい
て、約1秒と非常に長いことに着目し、子局の受信回路
に複数の制御情報用のバッファメモリを設け1機器制御
中にも親局からの次の制御信号を受は付けることによっ
て親局−子局間の迅速な伝送を図ったものである。
The present invention is a polling type information transmission device in which the selection signal from the master station to the slave stations is transmitted independently, and the operating time of the control relay is approximately 1 second in a powerful device. Focusing on the long length, we installed a buffer memory for multiple pieces of control information in the receiving circuit of the slave station, and even when one device is being controlled, the next control signal from the master station is received and attached, thereby speeding up the communication between the master station and the slave station. The aim is to ensure efficient transmission.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第1図ないし第7図により説
明する。第6図はシステム構成図、第5図は装置構成図
、第1図は本発明の伝送タイムチャート及び制御出力タ
イムチャートである。図において1は伝送を管理する中
央処理装置としての親局であり、2は親局とそれぞれの
子局3をつなぐ信号伝送装置である。又、子局3は信号
伝送装置2とつながるデータ送受信部4と複数のデータ
入出力部5及び送受信回路と複数の制御出力回路を結ぶ
バス11からなっている。
An embodiment of the present invention will be described below with reference to FIGS. 1 to 7. FIG. 6 is a system configuration diagram, FIG. 5 is an apparatus configuration diagram, and FIG. 1 is a transmission time chart and a control output time chart of the present invention. In the figure, 1 is a master station as a central processing unit that manages transmission, and 2 is a signal transmission device that connects the master station and each slave station 3. Further, the slave station 3 includes a data transmitting/receiving section 4 connected to the signal transmission device 2, a plurality of data input/output sections 5, and a bus 11 connecting the transmitting/receiving circuit and the plurality of control output circuits.

親局1からの機器選択信号は信号伝送装置2を介して、
子局3の送受信回路6に入力される。子局3ではマイク
ロプロセッサ7によりROMメモリ9のプログラムが起
動され、現在制御中の機器がないことを確認した上で外
部バス11を介し、受信した信号が該当する制御信号出
力回路5−i(1≦i≦n)に出力される。制御信号出
力回路5−iでは該当するCE12の選択リレーをON
し、選択完了信号を外部バス11を通じ、データ送受信
部4へ返す。マイクロプロセッサ7は制御信号出力回路
5−iからの選択完了信号を受けとると、送受信回路6
を通じ、選択応答信号を信号伝送装置2を介し、親局1
に送信する。親局1では、子局からの選択応答信号を受
は付けると、続いて制御信号を該当子局に送信する。親
局1からの制御信号を受信すると、子局3ではマイクロ
プロセッサにより選択されている制御出力回路5−iに
外部バスを介し、制御信号を出力すると同時に、親局1
に対し制御応答信号を送受信回路6により信号伝送装置
2を介して送信することにより、一連の伝送手順が終了
する。
The device selection signal from the master station 1 is sent via the signal transmission device 2.
The signal is input to the transmitting/receiving circuit 6 of the slave station 3. In the slave station 3, the program in the ROM memory 9 is started by the microprocessor 7, and after confirming that no device is currently being controlled, the received signal is sent to the corresponding control signal output circuit 5-i ( 1≦i≦n). The control signal output circuit 5-i turns on the selection relay of the corresponding CE12.
Then, a selection completion signal is returned to the data transmitting/receiving section 4 via the external bus 11. When the microprocessor 7 receives the selection completion signal from the control signal output circuit 5-i, it
, the selection response signal is sent to the master station 1 via the signal transmission device 2.
Send to. When the master station 1 receives the selection response signal from the slave station, it subsequently transmits a control signal to the slave station. Upon receiving the control signal from the master station 1, the slave station 3 outputs the control signal to the control output circuit 5-i selected by the microprocessor via the external bus, and at the same time outputs the control signal to the control output circuit 5-i selected by the microprocessor.
A series of transmission procedures is completed by transmitting a control response signal from the transmitting/receiving circuit 6 via the signal transmitting device 2.

次に、子局3からの制御応答信号を受信した親局1は、
他に制御対象となる機器があれば、続いて子局3に対し
別の機器選択信号を送信し、子局3では新たに機器選択
信号が信号伝送装置2を介し、送受信回路6に入力され
る。子局3ではマイクロプロセッサ7により、前の制御
信号が実行中の場合には、受信した機器選択信号に対応
した選択応答信号を送受信回路6及び信号伝送装置2を
介し、親°局1に送信する。親局1では選択応答信号S
Rを受信すると、更に、制御信号Eを子局3に対し送信
する。子局3は制御信号Eを受信すると、機器選択信号
Sとともに、RAMメモリ10の制御信号E用バッファ
メモリに格納すると同時に、親局1に制御応答信号ER
を送受信回路6、信号伝送装置2を介して返信を行なう
。親局1は子局3からの制御応答信号ERを受信すると
、更に、制御対象となる機器があれば上記手順を繰り返
す・ 一方、制御信号出力回路5−iでは、制御出力が終了し
、制御リレーがOFFした条件により、該当CEの選択
リレーをOFFに戻す。マイクロプロセッサ7は該当G
Eの選択リレーがOFFになり、全てのGEの選択リレ
ーがOFFであることを確認した上で、RAMメモリ1
0にある制御信号用バッファに制御信号情報が残ってい
れば、まず、制御信号用バッファより機器選択信号Sを
取り出し、外部バス11を介して該当する制御信号出力
回路5−i(1≦i≦n)に出力する。機器選択信号を
受は取った制御信号出力回路5−iでは、CEの該当リ
レーがONし1選択完了信号を外部バス11を通じ、プ
ロセッサ7へ出力する。
Next, the master station 1 that received the control response signal from the slave station 3,
If there is another device to be controlled, then another device selection signal is sent to the slave station 3, and the slave station 3 inputs a new device selection signal to the transmitter/receiver circuit 6 via the signal transmission device 2. Ru. In the slave station 3, the microprocessor 7 transmits a selection response signal corresponding to the received device selection signal to the master station 1 via the transmitter/receiver circuit 6 and the signal transmission device 2, if the previous control signal is being executed. do. At master station 1, selection response signal S
Upon receiving R, it further transmits a control signal E to the slave station 3. When the slave station 3 receives the control signal E, it stores it in the control signal E buffer memory of the RAM memory 10 together with the device selection signal S, and at the same time sends the control response signal ER to the master station 1.
A reply is sent via the transmitter/receiver circuit 6 and the signal transmission device 2. When the master station 1 receives the control response signal ER from the slave station 3, it repeats the above procedure if there is another device to be controlled. On the other hand, in the control signal output circuit 5-i, the control output ends and the control Depending on the conditions under which the relay was turned OFF, the selected relay of the corresponding CE is turned OFF. Microprocessor 7 corresponds to G
After confirming that the E selection relay is OFF and all GE selection relays are OFF, the RAM memory 1
If control signal information remains in the control signal buffer located at 0, first, the device selection signal S is taken out from the control signal buffer, and the corresponding control signal output circuit 5-i (1≦i ≦n). In the control signal output circuit 5-i which receives the device selection signal, the corresponding relay of the CE is turned on and outputs a 1 selection completion signal to the processor 7 through the external bus 11.

プロセッサ7は選択完了信号を受けとると、直ちに、制
御信号用バッファより制御信号を取り出し、該当制御信
号出力回路5−iに制御信号を出力する。該当制御信号
出力回路5−iは制御出力が終了し制御リレーがOFF
になる条件により該当GEの選択リレーをOFFに戻す
。この一連の動作をRAMメモリ10にある制御信号用
バッファに制御信号情報がなくなるまで繰り返す。
Upon receiving the selection completion signal, the processor 7 immediately takes out the control signal from the control signal buffer and outputs the control signal to the corresponding control signal output circuit 5-i. The control output of the corresponding control signal output circuit 5-i ends and the control relay turns OFF.
The selection relay of the corresponding GE is returned to OFF depending on the condition. This series of operations is repeated until there is no more control signal information in the control signal buffer in the RAM memory 10.

なお、図中8は内部バス。Note that 8 in the figure is an internal bus.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ポーリング方式の情報伝送装置におい
て、同一子局で連続した制御が行なわれた場合には、従
来の情報伝送装置よりも伝送時間が大幅に短縮された迅
速な伝送制御が行えるので、システム全体の機能が向上
する。
According to the present invention, in a polling type information transmission device, when the same slave station performs continuous control, it is possible to perform quick transmission control with a significantly shorter transmission time than in a conventional information transmission device. Therefore, the functionality of the entire system is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による伝送及び制御信号出力タイムチャ
ート、第2図は制御信号受信プログラム図、第3図は制
御信号格納プログラム図、第4図は制御信号出力プログ
ラム図、第5図は情報伝送装置構成)図、第6図はシス
テム構成図、第7図は従来の伝送及び制御信号出力タイ
ムチャートである。 1・・・親局、2・・・信号伝送装置、3・・・子局、
4・・・データ送受信部、5・・・データ入出力部、6
・・・送受信回路、7・・・マイクロプロセッサ、8・
・・内部バス、9・・・POM、10・・・RAM、1
1・・・外部バス、12、CE、13・・・入出力回路
Figure 1 is a transmission and control signal output time chart according to the present invention, Figure 2 is a control signal reception program diagram, Figure 3 is a control signal storage program diagram, Figure 4 is a control signal output program diagram, and Figure 5 is an information FIG. 6 is a system configuration diagram, and FIG. 7 is a conventional transmission and control signal output time chart. 1... Master station, 2... Signal transmission device, 3... Slave station,
4...Data transmission/reception section, 5...Data input/output section, 6
... Transmission/reception circuit, 7... Microprocessor, 8.
...Internal bus, 9...POM, 10...RAM, 1
1...External bus, 12, CE, 13...I/O circuit.

Claims (1)

【特許請求の範囲】 1、伝送回線を介してポーリング方式により、親局に接
続され、信号伝送装置とデータの送受信を行う送受信回
路と、その送受信回路を制御するマイクロプロセッサと
、このマイクロプロセッサとバス結合により接続される
プロセス出力コントロールエレクトロニクスとプロセス
入出力装置とから構成される制御出力回路からなる情報
伝送装置において、 前記親局から送信してくる前記情報伝送装置の前記制御
出力回路に対する機器選択信号と制御信号を一時的に記
憶する複数のバッファメモリを設け、前記機器選択信号
を受信時に前記制御出力回路が動作中の場合は、受信し
た前記機器選択信号に対応する機器選択応答信号を前記
親局に返送し、前記制御信号を受信すると、前記機器選
択信号と共に前記バッファメモリに格納し、格納後前記
親局に制御応答信号を送信し、更に、次の機器制御信号
の受信を上述の手順で再開し、又、前記親局からの前記
機器制御信号がなければ、前記バッファメモリに格納さ
れた前記機器制御信号を順次前記バッファメモリから取
り出し、前記制御出力回路に出力することを特徴とする
遠方監視制御方法。
[Claims] 1. A transmitting/receiving circuit that is connected to a master station by a polling method via a transmission line and transmits and receives data to and from a signal transmission device, a microprocessor that controls the transmitting/receiving circuit, and this microprocessor. In an information transmission device comprising a control output circuit comprising process output control electronics and a process input/output device connected by bus coupling, equipment selection for the control output circuit of the information transmission device transmitted from the master station is provided. A plurality of buffer memories for temporarily storing signals and control signals are provided, and if the control output circuit is in operation when receiving the device selection signal, the device selection response signal corresponding to the received device selection signal is transmitted to the device selection signal. When the control signal is received, it is stored in the buffer memory together with the device selection signal, and after storage, a control response signal is transmitted to the master station, and furthermore, the reception of the next device control signal is controlled by the above-mentioned method. If the device control signal is restarted according to the procedure and there is no device control signal from the master station, the device control signal stored in the buffer memory is sequentially retrieved from the buffer memory and output to the control output circuit. A remote monitoring and control method.
JP59199604A 1984-09-26 1984-09-26 Remote supervisory controlling method Pending JPS6178244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59199604A JPS6178244A (en) 1984-09-26 1984-09-26 Remote supervisory controlling method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59199604A JPS6178244A (en) 1984-09-26 1984-09-26 Remote supervisory controlling method

Publications (1)

Publication Number Publication Date
JPS6178244A true JPS6178244A (en) 1986-04-21

Family

ID=16410619

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59199604A Pending JPS6178244A (en) 1984-09-26 1984-09-26 Remote supervisory controlling method

Country Status (1)

Country Link
JP (1) JPS6178244A (en)

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