JPS6177469A - Thermal head driver circuit - Google Patents

Abstract

PURPOSE:To transfer data to a thermal head of alternate read system at a high speed by considering four data bits to be one block and re-arraying data in said one block. CONSTITUTION:When a lateral dot string to be printed is inputted by four bits D0-D3 and a common terminal C1 supplies the printing electric power in correspondence to the 1st selection signal, the bits D0 and D3 are outputted to the serial input terminal of a sequential shift register S synchronous to the 2nd selection signal. When common terminal C2 supplies the printing electric power, the bits D1 and D3 are inputted to the serial input terminal of the shift register S synchronous to the 2nd selection signal. Thus printed data of a line type thermal head of alternate system can be transferred at a high speed. Thus single-colored printing and colored printing at multi-gradation can be carried out easily at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a printer equipped with an alternating lead type line type thermal head.

(Prior art) In a printer equipped with a line-type thermal head,
Alternating lead type thermal heads are often used. In the alternate read method, adjacent elements are made to function alternately by dividing the power strobe line into several blocks or using the same data line in time series to reduce the number of data lines. Data processing is performed in two parts instead of processing one line of printing at once. By using this alternate lead method, the resolution of printed dots can be improved and the number of lead wires from the head substrate can be reduced.

FIG. 6 is a circuit diagram of an example of an alternate read type head driver. Thermal heating resistor T is a single heat generating resistor, and a diode D and a NAND output terminal are alternately connected from the left end to electrode terminals provided at regular intervals perpendicularly to the heat generating resistor. The opening of each connection point is an element that is individually energized for heat generation, and each element is numbered 1, 2, 3, etc. from the left side. It is numbered by...

Each diode D connects the common terminals C1 and C alternately from the left side.
2 and 1 are connected. The output terminals of the shift register S arranged from left to right are sequentially connected to one input terminal of each NAND gate. Data is input to the shift register S from the right side.

The Ikekata input terminals of each NAND date are commonly connected every 4 input terminals from the left end, and then the strobe 5T
RI, 5TR2,-=, connected to 5TRn.

In this driver circuit, when the output terminal of the NAND date is at a low level and the common terminal C1 or C2 is at a high level, current flows through the element connected between them, heating the element, and The thermal recording paper that is close to the reacts. When driving the thermal head, by alternately setting the common terminals C1 and C2 to a high level, adjacent elements are made to function alternately. The data line is prepared serially at the input terminal "IN" of the shift register, and is sequentially shifted and inputted by the clock pulse CP, and is latched when the input is completed.Up to this stage, the strobes 5TRI, 5TR2°, etc.・, 5TRn is set to low level so that the output of any date does not become low level.Next, strobes 5TRI and 5TR are set to low level.
2,...,5TRn is set to a high level (if the capacity of the power supply is limited, set each strobe to a high level several times if necessary), the common terminal that is at a high level Current flows from the output terminal of the NAND date, which is at a low level, through the intervening elements.

The element becomes hot, and recording is performed on thermal recording paper by thermal transfer.

(Problems to be Solved by the Invention) Adopting the alternate read method has advantages such as halving the capacity of the shift register and reducing the power supply capacity. However, when driving an alternate read type header and transferring data to a shift register S, complicated and complicated management must be performed as described below.

As shown in FIG. 2, in the alternate read type head driver, the addresses of the elements (C1 assert elements) that can be driven by the common terminal C1 are 1, 4, 5 degrees, 8.9 degrees, 12 degrees, .・
..., that is, when n is an integer, 2n (1-
(-1)n)/2. On the other hand, the addresses of the elements (C2 assert elements) that can be driven by the common terminal C2 are 2, 3,
6, 7, 10, 11. ...That is, 2n (1+
(1)0)/2. Therefore, when driving the C1 assert element, the shift register S includes elements 1, 1,
4, 5, 8. I have to enter data for... On the other hand, when driving the C2 assert element, elements 2, 3 degrees 6.7, 10 . I have to enter data for... That is, before inputting the data to the shift register, such complicated data rearrangement must be performed. In this operation, it takes a considerable amount of time to find, search, and process the element address from the relational expression.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thermal driver circuit capable of high-speed thermal-to-thermal data transfer using an alternating read method.

(Means and effects for solving the problem) The present inventor takes the interpretation of the regularity of data rearrangement one step further, considers four data bits as one block, and within this one block, the data is We have discovered that by rearranging the arrangement, it is possible to realize an alternate read type head drive with a simple circuit configuration.

In the driver circuit of the alternating lead type thermal head according to the first invention of the present application, a first common terminal and a second common terminal that supply printing power from printing data to a linear resistance heating element are arranged alternately. The output data of the shift register, which is printing information, is connected in sequence between these connection points, and the first common terminal and the second common terminal sequentially supply printing power to form one horizontal dot. In the driver circuit of an alternating read type thermal head that prints a row of dots, the horizontal dot row to be printed is 4 bits D. +DIld2.
D, is input in units of 1 to 1 earth when the first common terminal supplies printing power, corresponding to the first selection signal indicating which of the first common terminal and the second common terminal supplies printing power. , 4-bi-nt. and D3 are sequentially output to the serial input terminal of the shift register by a second selection signal synchronized with the clock pulse of the shift register, and when supplied from the second common terminal, D1 and D2 among the four bits are output to the second selection signal. The present invention is characterized in that a data conversion circuit is provided which outputs the data to the serial input terminal of the shift register in synchronization with the selection signal.

The horizontal dot row to be printed is input in two parts to a shift register that stores print data for driving the alternate read type thermal head. In the data conversion circuit according to the present invention, rearranging the data of the horizontal dot row converts the horizontal dot row into 4 bits D0, D1, D2 . It is input and processed sequentially in units of D. 4 bits when the first common terminal supplies power. ID) are sequentially transferred to the shift register, and by repeating this process, all the 2n-(1(1)n)/2nd bits of the horizontal dot string are transferred to the shift register. Also, when power is supplied from the second common terminal, D=D of the 4 bits.
2 are sequentially transferred to the shift register, and by repeating this process, 2n (1+(1)n)/
All second bits will be transferred to the shift register. In this way, the rearrangement of the horizontal dot rows when they are transferred to the shift register can be performed with a simple circuit configuration.

Further, in the driver circuit of the mutual read type thermal head according to the second invention of the present application, there is further provided a gradation modulation means for converting the (NXN) matrix into binary data using the dot density modulation method. will be added. The minimum unit of the number of pixels processed by this gradation modulation means is L/N, where L is the least common multiple of N and 4. Then, the gradation modulation means outputs the L-bit horizontal dot string of the L-bit binarized data to the data conversion means, and the data conversion means converts the L bits as in the first invention. Processing is performed in units of 4 dots (Do, DI, D2.D,).

(Example) If we consider the elements of the resistance heating element in blocks of 4 pins as shown in Fig. 2, in each block, the C1 assert element is the element at both ends, and the C27 assert element is the element at the inner side. There are two elements. For example, in the first block, the C1 assert elements are the first and fourth elements, and the C2 assert elements are the second and third elements. Therefore, the data in the first block is M, , M, , M2 . M, when driving with the common terminal C1, data M. It is sufficient to store them in the shift register S in the order of 1M3. Furthermore, when driving with the common terminal C2, data M, , M2 may be sequentially stored in the shift register S in this order.

As shown in FIG. 1, this data array conversion can be realized, for example, by a simple circuit configuration using a data selector (74LS253) DS, without using software. Data selector DS input terminal 0
, D1, D2. Data bits A, B, C, and D assigned to a block of four elements are input to D3. At this time, as shown in Fig. 3, A becomes Do, Dli:D,
C.

Then, cross-input D to D2. Note that the data bits A, B, C, and D are given, for example, by sequential output in units of 4 bits from a character generator or a bitmap (not shown). The output terminal Y is connected to the serial input terminal D1N of the shift register S. The selection input terminal SA receives the clock pulse CP of the shift register S.
A synchronized signal is input. The selection input terminal SB is
When driven by the common terminal C1, it is connected to a low level L, and when driven by the common terminal C2, it is connected to a high level H. ○
The C terminal is grounded. FIG. 3 is a truth table of the data selector DS. In the driver circuit shown in FIG. 3, when driving the C1 assert element, the selection input terminal SB is set to a low level. and,
When the other selection input terminal SA is synchronized with the clock pulse of the shift register S, first to a low level L and then to a high level H, A and D are sequentially output to the output terminal Y.
The shift register S is manually operated. Similarly, when driving the C2 assert element, select input terminal SA is set to high level. Then, the other selection input terminal SB is connected to a low level L in synchronization with the clock pulse CP of the shift register S.
Then, when the next high level is set to H, B and C are output to output terminal Y in sequence.
is output and input to the shift register S. In this way, the bit arrangement of the print data is changed from A; B, C, D to A.
, D, B, C and data selector DSt-A, D
Alternatively, by sequentially outputting B and C, high-speed data conversion becomes possible. Note that a circuit configuration in which a plurality of blocks overlap can be used. Furthermore, if the shift register is divided into a plurality of sets and processed, data can be converted even faster.

Next, an embodiment (see FIG. 4) for printing a multi-gradation image made possible by this high-speed data transfer will be described. One of the methods for digitally recording multi-tone images using monochrome or multi-color binary data is the density pattern method, which reproduces pseudo-halftones by dot density modulation. The systematic dither method is a typical density pattern method. In the systematic dither method, one pixel is associated with an NXN matrix,
The density signal (gradation signal) at each element of the matrix is binarized using a type of pseudo-random number (referred to as a dither matrix) as a threshold. Using a Bayer matrix (Figure 5), which is a typical dither matrix, for example, when the density signal of the (2,2) element of a pixel is greater than 8,
It is judged that. In this embodiment, the gray level signal is binarized into dot image bits of an NXN matrix via a look amplifier table, and output as a horizontal dot array of a dot density modulated dot image.

By the way, in the density pattern method, one pixel consists of N horizontal dots,
It consists of a dot set of tIIN dots, and this dot set is expressed as an NXN matrix. In a line type thermal head printer, the common terminals CI and C2 are selected alternately, and a horizontal dot row of N dots per pixel is sequentially
By recording on a daily basis, a density pattern for one pixel is recorded.

In the reciprocal read type head driver according to the present invention, as described above, a horizontal dot row of four dots is treated as one block. For convenience, in the configuration of the minimum unit of gradation modulation that converts pixel gray signals into dot image bits of an N Let it be the least common multiple of a certain N and 4, and therefore, let L/N be the number of pixels whose gradation is converted at the same time. For example, (1) in the case of a 2x2 matrix, L=4, and the lookup table outputs in units of 4 focal points for 2 consecutive pixels. (2) In the case of a 3×3 matrix, L=12, and the lookup table outputs in units of 12 bits for four consecutive pixels. (3)4
In the case of an
It is output from the lookup table in units of bits.

The embodiment shown in FIG. 4 corresponds to the case of a 4×4 matrix. The 4-bit gray scale human input signal is input to the look amplifier table input terminals A2, A. ,A4,A,, 4×4
The dot image bits of the matrix are converted into horizontal dot rows and sent to output terminal O. ,011○2.

○, is output. Each output terminal○,,0110210,
are the input terminals of the data selector DS, respectively. I
C2 1 Di I Connected to DI in a sash. The data selector DS is 74 as in the case of FIG.
LS253 is used. The selection input terminal SA receives a signal synchronized with the clock pulse CP of the shift reno star S, and the selection input terminal SB receives the common terminals C1. A signal for selecting C2 is input.

In this example, input terminal A2+ AH A4HA
, 4-bit gradation data P. ,P2,P,,P.

When input, it is converted into a dot image bit by the lookup table LT and sent to the output terminal O. , 01.

02, 0. is output to. And data selector DS
Input appropriate signals to the selection input terminals SA and SB with 00
01 and 02 are sequentially output to the serial input terminal DIN of the shift register S.

(Effects of the Invention) According to the present invention, it is possible to transfer print data at high speed to an alternate read type line type thermal head, and a high speed printer can be provided.

As a result, multi-tone monochrome and color printing can be performed quickly and easily. Furthermore, by using the remaining addresses in the lookup table, various gradation correction processes are now possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention. FIG. 2 is a diagram showing the relationship between elements and alternate processing. FIG. 3 is a truth table of the data selector. FIG. 4 is a circuit diagram of an embodiment of the pond of the present invention. FIG. 5 shows a Bayer type dither matrix. FIG. 6 is a circuit diagram of a conventional alternate lead type thermal head driver. LT... Lookup table, DS... Data selector. Patent applicant Minolta Camera Co., Ltd. Representative
Person Patent Attorney Blue and White Mug Two Idiots IN1 Figure 2I71 3 Figure II5 r4 Figure 6 Well JL Shizuko GNDζ-1000

Claims (2)

[Claims] (1) A first common terminal and a second common terminal that supply printing power are alternately connected to the linear resistance heating element, and
The output data of the shift register, which is printing information, is connected in the middle of each of these connection points, and the first common terminal and the second common terminal sequentially supply printing power to alternate leads that print one horizontal dot row. In the driver circuit of the thermal head, the horizontal dot row to be printed is 4 bits D_0_~_
3. The first common terminal supplies the power in response to the first selection signal that is input in units of D_1, D_2, and D_3 and indicates which of the first common terminal and the second common terminal supplies printing power. Sometimes, D_0 and D_3 of the 4 bits are sequentially output to the serial input terminal of the shift register in response to a second selection signal synchronized with the clock pulse of the shift register, and when the second common terminal supplies the 4 bits. A driver circuit characterized in that a data conversion circuit is provided in which data D_1 and D_2 are sequentially outputted to a serial input terminal of a shift register in response to a second selection signal. (2) A first common terminal and a second common terminal that supply printing power are alternately connected to the linear resistance heating element, and
The output data of the shift register, which is printing information, is connected in the middle of each of these connection points, and the first common terminal and the second common terminal sequentially supply printing power to alternate leads that print one horizontal dot row. In the driver circuit of the thermal head, there is a gradation modulation means that converts the gradation signal into binary data of an (N×N) matrix using the dot density modulation method, and a horizontal dot row to be printed is 4 bits D_0, D_
When the first common terminal supplies printing power in response to a first selection signal that is input in units of 1, D_2, and D_3 and indicates which of the first common terminal and the second common terminal supplies printing power, Out of the 4 bits, D_0 and D_3 are sequentially output to the serial input terminal of the shift register in response to the second selection signal synchronized with the clock pulse of the shift register. D
Data conversion means is provided in which _1 and D_2 are sequentially outputted to the serial input terminal of the shift register in response to the second selection signal, and the minimum unit of the number of pixels processed by the above-mentioned gradation modulation means is N and 4. When L is the least common multiple of 4 dots (D_0, D_
1, D_2, D_3).