JPS6177352A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6177352A JPS6177352A JP59198361A JP19836184A JPS6177352A JP S6177352 A JPS6177352 A JP S6177352A JP 59198361 A JP59198361 A JP 59198361A JP 19836184 A JP19836184 A JP 19836184A JP S6177352 A JPS6177352 A JP S6177352A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- chips
- scribe line
- chip
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06551—Conductive connections on the side of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関する。特に、半導
体装置チップを複数個積層し、各チップ相互間を接続し
て、複数のチップをもって単一の半導体装置を構成する
チップオンチップ型ＩＣの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a chip-on-chip type IC in which a plurality of semiconductor device chips are stacked and the chips are interconnected to form a single semiconductor device.
半導体装置の集積度を向上するため、半導体装置チップ
を複数個積層して単一の半導体装置を構成することが提
案されている。本発明は、か−るチップオンチップ型Ｉ
Ｃ構造の半導体装置の製造方法に関する。In order to improve the degree of integration of semiconductor devices, it has been proposed to stack a plurality of semiconductor device chips to form a single semiconductor device. The present invention provides a chip-on-chip type I
The present invention relates to a method of manufacturing a C-structure semiconductor device.
従来技術においては、半導体装置チップと外部との接続
にはポンディングワイヤが使用されていた。複数のチッ
プを積層して単一の半導体装置を構成するチップオンチ
ップ構造の場合、チップ相互間の接続が必要であるが、
これをポンディングワイヤを使用して実現することはで
きず、チップ相互を接続するために、何らかの手段の開
発が望まれていた。In the prior art, bonding wires have been used to connect semiconductor device chips to the outside. In the case of a chip-on-chip structure in which multiple chips are stacked to form a single semiconductor device, connections between the chips are required.
This cannot be achieved using bonding wires, and it has been desired to develop some means for interconnecting the chips.
本発明は、この要請にこたえ、ポンディングワイヤを使
用せずにチップ相互間の接続をなすことが可能である、
半導体装置チップ積層方式の半導体装置の製造方法を提
供するものであり、その手段は、半導体装置用ウェーハ
のスクライブライン上に、該スクライブラインをまたい
で複数の貫通孔を形成し、該貫通孔中に金属埋め込み層
を形成し、同時に、該金属埋め込み層と所望の電極・配
線とを接続し、前記ウェーハを前記スクライブラインに
そって切断して周辺部に前記金属埋め込み層を有する複
数の半導体装置チップを形成し、該チップの複数個を前
記金属埋め込み層が相互に接触するように積層する工程
を有する半導体装置の製造方法と、半導体装置用ウェー
ハのスクライブライン上に、該スクライブラインをまた
いで、複数の貫通孔を形成し、該貫通孔の内面に金属層
を形成し、同時に、該金属層と所望の電極・配線とを接
続し、前記ウェーハを前記スクライブラインにそって切
断して、内面に前記金属層を有する凹部を周辺部に有す
る複数の半導体装置チップを形成し、前記凹部に対応す
る領域に導電体棒を有するパッケージ中に、前記チップ
の複数個を前記導電体棒と前記凹部とが係合接触するよ
うに積層収納する工程を有する半導体装置の製造方法と
にある。The present invention responds to this demand by making it possible to connect chips to each other without using bonding wires.
The present invention provides a method for manufacturing a semiconductor device using a semiconductor device chip stacking method, and the method includes forming a plurality of through holes on a scribe line of a semiconductor device wafer, straddling the scribe line, and forming a plurality of through holes in the through hole. forming a metal buried layer on the wafer, simultaneously connecting the metal buried layer to desired electrodes/wirings, and cutting the wafer along the scribe line to form a plurality of semiconductor devices having the metal buried layer in the peripheral portion. A method for manufacturing a semiconductor device comprising the steps of forming a chip and stacking a plurality of the chips so that the metal embedded layers are in contact with each other; , forming a plurality of through holes, forming a metal layer on the inner surface of the through holes, simultaneously connecting the metal layer to a desired electrode/wiring, and cutting the wafer along the scribe line; A plurality of semiconductor device chips each having a concave portion having the metal layer on the inner surface at the periphery thereof is formed, and a plurality of the chips are placed in a package having a conductive bar in a region corresponding to the concave portion. The semiconductor device manufacturing method includes the step of stacking and storing the semiconductor device so that the semiconductor device and the recess are in engagement contact with each other.
本発明は、半導体装置チップの周辺部の側面から上下面
にかけて導電性接続部を設け、チップを積層したときこ
れらの導電性接続部が互いに接触するようにするもの（
特許請求の範囲第１項）と、上記の導電性接続部はチッ
プの周辺部に設けられた凹部の内面に設け、一方、チッ
プ積層体が収容されるパッケージには、上記の凹部に対
応するように導電体棒を設けておき、チップ積層体をパ
ッケージに収納するにあたり、この導電体棒と」二記の
凹部とを係合させることとして、導電□体棒と凹部との
組み合わせをもって治具的機能と接続機能との双方を兼
ねさせるもの（特許請求の範囲第２項）とであり、これ
を実現するために、特許請求の範囲第１項の発明にあっ
ては、第２図に示すように、半導体装置用ウェーハｌの
スクライブライン２上に、スクライブライン２をまたい
で（チップ領域に進入するように）貫通孔３を形成した
後、第３図に示すように、この貫通孔３と金属埋め込み
層４をもって埋め、同時に、この金属埋め込み層４と所
望の電極ｅ配線５とを接続し、第４図に示すように、各
チップを切り離して周辺部に導電性接続部４を有するチ
ー２プロを複数個形成し、第５図に示すように、周辺の
導電性接続部４が互いに接触するように、これらのチッ
プ６を積層するものであり、特許請求の範囲第２項の発
明にあっては、第２図に示すように、半導体装置用ウェ
ーハｌのスクライブライン２１に、スクライブライン２
をまたいで（チップ領域に進入するように）貫通孔３を
形成した後、第６図に示すように、この貫通孔３の内面
と貫通孔３周辺の上下面とに金属層１０を形成し、同時
に、この金属層１０と所望の電極・配線５とを接続し、
第７図に示すように、各チップを切り離して、周辺部に
その内面が導電性接続部ｌＯとされている凹部３′を有
するチップ１１を複数個形成し、一方、第８図に示すよ
うに、上記の凹部３°と対応する領域に導電体棒１３が
設けられたパッケージ１４を形成し、第１図（ｂ）、（
ｃ）に示すように、凹部３゛と導電体棒１３とが係合す
るように組み立てて、接続を実現するものである。The present invention provides conductive connecting portions from the side surfaces of the peripheral portion of a semiconductor device chip to the upper and lower surfaces so that these conductive connecting portions come into contact with each other when the chips are stacked (
(Claim 1), the above-mentioned conductive connection portion is provided on the inner surface of a recess provided at the periphery of the chip, while the package in which the chip stack is accommodated has a structure corresponding to the above-mentioned recess. A conductor rod is provided as shown in FIG. In order to realize this, the invention as claimed in claim 1 has the functions shown in Fig. 2. As shown in FIG. 3, after forming a through hole 3 on the scribe line 2 of the semiconductor device wafer l, straddling the scribe line 2 (so as to enter the chip area), the through hole 3 is formed as shown in FIG. 3 and a metal buried layer 4, and at the same time connect this metal buried layer 4 to a desired electrode e-wiring 5. As shown in FIG. As shown in FIG. 5, these chips 6 are stacked so that the peripheral conductive connection parts 4 are in contact with each other. In the invention, as shown in FIG.
After forming a through hole 3 across the substrate (so as to enter the chip area), a metal layer 10 is formed on the inner surface of the through hole 3 and the upper and lower surfaces around the through hole 3, as shown in FIG. , At the same time, connect this metal layer 10 to a desired electrode/wiring 5,
As shown in FIG. 7, each chip is separated and a plurality of chips 11 having recesses 3' whose inner surfaces are used as conductive connection parts 10 are formed at the periphery, and on the other hand, as shown in FIG. Then, a package 14 in which a conductor rod 13 is provided in a region corresponding to the 3° concave portion is formed, and as shown in FIG. 1(b), (
As shown in c), the connection is achieved by assembling the recess 3' and the conductor rod 13 so that they engage with each other.
以下、図面を参照しつ一１本出願に係るそれぞれの発明
に係る実施例について、さらに説明する。Hereinafter, embodiments of each of the inventions of the present application will be further described with reference to the drawings.
第２図参照
半導体装置用ウェーハｌのスクライブライン２上に、ス
クライブライン２をまたいで複数の貫通孔３を形成する
。スクライブライン２は２００〜３００ＪＬ１１程度の
幅とすることが一般であるが、貫通孔３は、スクライブ
ライン２をまたいで、チップ領域に １００ ｐ、 ｍ
程度づつ進入するように。Referring to FIG. 2, a plurality of through holes 3 are formed on the scribe line 2 of the wafer l for semiconductor devices, straddling the scribe line 2. Generally, the scribe line 2 has a width of about 200 to 300 JL11, but the through hole 3 straddles the scribe line 2 and has a width of 100 p, m in the chip area.
Try to enter it gradually.
４００〜５００ ｇ ｍ程度の幅に形成する。この工程
は、通常のフォトリソグラフィー法とケミカルエツチン
グ法とを使用して容易に実行しうる。It is formed to a width of about 400 to 500 gm. This step can be easily performed using conventional photolithography and chemical etching methods.
第３図参照
つＣいて、貫通孔３中にアルミニウム等を埋め込むが、
このとき、埋め込み層４はチップの上面を伸延させ所望
の電極・配線５と接続する。この工程はアルミニウム蒸
着法を使用してなすリフトオフ法を使用して容易に実行
しうる。Referring to FIG. 3, aluminum or the like is embedded in the through hole 3.
At this time, the buried layer 4 extends the top surface of the chip and connects to the desired electrode/wiring 5. This step can be easily performed using a lift-off method using aluminum vapor deposition.
第４図、第５図参照
ウェーハｌをスクライブライン２にそって切断して、周
辺部にアルミニウム埋め込み層４よりなる導電性接続部
を有する半導体装置チップ６を複数個製造する。Referring to FIGS. 4 and 5, the wafer 1 is cut along the scribe line 2 to produce a plurality of semiconductor device chips 6 each having a conductive connection portion made of an aluminum buried layer 4 at the periphery.
これらのチップ６を積層する。このとき、第４図に示す
平面図のＡ−Ａ断面図（第５図）に示すように、アルミ
ニウム埋め込み層４が相互に接触するようにする。積層
したチップ６の固着は接着法をもって容易に可能である
。These chips 6 are stacked. At this time, the aluminum buried layers 4 are brought into contact with each other, as shown in the AA sectional view (FIG. 5) of the plan view shown in FIG. The stacked chips 6 can be easily fixed using an adhesive method.
第１図（ａ）参照
パッケージはセラミックパッケージでもプラスチックパ
ッケージでも金属パッケージでもさしつかえないが、１
例としてプラスチックパッケージを使用する場合を示す
、チップ６の積層体をリードフレーム７上に取り付け、
ワイヤ８をワイヤポンドし、モールディングをなしてモ
ールドパッケージ９を形成し、リードフレームを切り離
して半導体装置を完成する。The package shown in Figure 1(a) may be a ceramic package, a plastic package, or a metal package, but 1
As an example, a stack of chips 6 is mounted on a lead frame 7, showing a case where a plastic package is used.
The wire 8 is wire bonded and molded to form a mold package 9, and the lead frame is separated to complete the semiconductor device.
以上の工程をもって、積層されたチップ相互間の接続は
ポンディングワイヤによらず、周辺部に設けられた導電
性接続部４をもってなし、過大の平面積を必要とせず、
集積度が十分に向上している半導体装置を製造すること
ができる。With the above steps, the stacked chips are connected to each other not by bonding wires but by the conductive connecting portions 4 provided at the periphery, and an excessively large planar area is not required.
A semiconductor device with a sufficiently improved degree of integration can be manufactured.
第２図参照
半導体装置用ウェーハｌのスクライブライン２上に、ス
クライブライン２をまたいで複数の貫通孔３を形成する
。スクライブライン２は２００〜３００ＪＬｍ程度の幅
とする場合が一般であるが、貫通孔３は、スクライブラ
イン２をまたいで、チップ領域に １１００ｐ程度づつ
進入するように、４００〜５００ ｇ ｍ程度の幅に形
成する。この工程は、通常のフォトリソグラフィー法と
ケミカルエツチング法とを使用して容易に実行しうる。Referring to FIG. 2, a plurality of through holes 3 are formed on the scribe line 2 of the wafer l for semiconductor devices, straddling the scribe line 2. Generally, the scribe line 2 has a width of about 200 to 300 JLm, but the through hole 3 has a width of about 400 to 500 gm so that it straddles the scribe line 2 and enters the chip area by about 1100 p. to form. This step can be easily performed using conventional photolithography and chemical etching methods.
第６図参照
貫通孔３の内面にアルミニウム等を蒸着またはメッキし
てアルミニウムの薄層１０を形成するが、このアルミ１
ニウムの薄層１０はチップの上面を伸延させ所望の電極
・配線５と接続する。Referring to FIG. 6, a thin layer of aluminum 10 is formed by vapor depositing or plating aluminum on the inner surface of the through hole 3.
A thin layer 10 of Ni extends the top surface of the chip and connects with the desired electrodes/wirings 5.
第７図参照
ウェーハｌをスクライブライン２にそって切断して、内
面にアルミニウムの薄層ｌＯよりなる凹状導電性接続部
３°を有するチップ１１を複数個製造する。Referring to FIG. 7, the wafer 1 is cut along the scribe line 2 to produce a plurality of chips 11 each having a concave conductive connection portion 3° made of a thin aluminum layer 10 on the inner surface.
第８図参照
一方、上記のチップ１１が密着して挿入されうる凹部１
２を有し、導電体棒１３が上記の凹状導電性接続部３′
に対応する領域に設けられているセラミックパッケージ
１４を形成する。ｌはスルーホールを介して接続される
外部引き出し端子である。Refer to FIG. 8. On the other hand, there is a recess 1 into which the chip 11 can be inserted closely.
2, and the conductor rod 13 is connected to the recessed conductive connection portion 3'.
A ceramic package 14 is formed in a region corresponding to the region. 1 is an external lead terminal connected via a through hole.
第１図（ｂ）、（Ｃ）参照
上記のチップ１１を、上記のパッケージ１４中に、凹状
導電性接続部３°と導電体棒１３とが接触するように、
挿入積層し、ポンディングワイヤ１５を施す。Refer to FIGS. 1(b) and 1(C). The above-mentioned chip 11 is placed in the above-mentioned package 14 so that the concave conductive connecting portion 3° and the conductive bar 13 are in contact with each other.
It is inserted and laminated, and a bonding wire 15 is applied.
以上の工程をもって、積層されたチップ相互間の接続は
ポンディングワイヤによらず、周辺部に設けられた凹状
導電性接続部３°と導電体棒１３との組み合わせをもっ
てなし、過大の平面積を必要とせず、集積度が十分に向
上している半導体装置を製造することができる。With the above process, the connection between the stacked chips is achieved not by bonding wires, but by the combination of the concave conductive connection part 3° provided at the periphery and the conductor rod 13, thereby reducing the excessive planar area. It is possible to manufacture a semiconductor device with a sufficiently improved degree of integration without the need for this.
以上説明せるとおり、本発明によれば、ポンディングワ
イヤを使用せずにチップ相互間の接続をなすことが可能
である、半導体装置チップ積層方式の半導体装置の製造
方法を提供することができる。As described above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor device using a semiconductor device chip stacking method, which allows connections between chips to be made without using bonding wires.
第１図（ａ）は、特許請求の範囲第１項記載の半導体装
置の製造方法の完了後の概念的構成図（横断面図）であ
る。第１図（ｂ）、（Ｃ）は、特許請求の範囲第２項記
載の半導体装置の製造方法の完了後の横断面図と平面図
である。第２図。
第３図、第４図、第５図は、特許請求の範囲第１項記載
の半導体装置の製造方法の重要工程完了後の、それぞれ
、ウェーハ平面図、ウェーハ平面図、チップ平面図、チ
ップ積層体横断面図である。第６図、第７図、第８図は
、特許請求の範囲第２項記載の半導体装置の製造方法の
重要工程完了後の、それぞれ、ウェーハ平面図、チップ
平面図、パッケージ横断面図である。
１Ｉ１１１−ウェーハ、 ２−・・スクライブライン、
３・・・貫通孔、 ３° ・争−凹状導電性接続部、
４・・・埋め込み層（導電性接続部）、 ５・・・電
極・配線、 ６・・・チツプ、 ７・・・リードフレ
ーム、 ３ ｍ ＊ ＊ポンディングワイヤ、
９ｅ・−モールドパッケージ、 １０・・晦アルミニ
ウムの薄層、 １１會・ｅチップ、 １２−・・凹部、
１３・・・導電体棒、１４・Φ・セラミックパッケー
ジ、 １５・・・ポン第５図
弓
第７図FIG. 1(a) is a conceptual configuration diagram (cross-sectional view) after completion of the method for manufacturing a semiconductor device according to claim 1. FIGS. 1(b) and 1(C) are a cross-sectional view and a plan view after completion of the method for manufacturing a semiconductor device according to claim 2. Figure 2. 3, 4, and 5 are a wafer plan view, a wafer plan view, a chip plan view, and a chip stacking diagram, respectively, after the important steps of the method for manufacturing a semiconductor device according to claim 1 are completed. It is a cross-sectional view of the body. FIG. 6, FIG. 7, and FIG. 8 are a wafer plan view, a chip plan view, and a package cross-sectional view, respectively, after the important steps of the method for manufacturing a semiconductor device according to claim 2 are completed. . 1I111-Wafer, 2-...Scribe line,
3...through hole, 3° - concave conductive connection part,
4... Buried layer (conductive connection part), 5... Electrode/wiring, 6... Chip, 7... Lead frame, 3 m * * Ponding wire,
9e--Mold package, 10--Thin aluminum layer, 11--E chip, 12--Concave part,
13... Conductor rod, 14 Φ Ceramic package, 15... Pon Figure 5 Bow Figure 7
Claims (2)
該スクライブラインをまたいで複数の貫通孔を形成し、
該貫通孔中に金属埋め込み層を形成し、同時に、該金属
埋め込み層と所望の電極・配線とを接続し、前記ウェー
ハを前記スクライブラインにそって切断して周辺部に前
記金属埋め込み層を有する複数の半導体装置チップを形
成し、該チップの複数個を前記金属埋め込み層が相互に
接触するように積層する工程を有する半導体装置の製造
方法。(1) On the scribe line of the wafer for semiconductor devices,
forming a plurality of through holes across the scribe line;
A metal buried layer is formed in the through hole, and at the same time, the metal buried layer is connected to a desired electrode/wiring, and the wafer is cut along the scribe line to have the metal buried layer in the peripheral portion. A method for manufacturing a semiconductor device, comprising the steps of forming a plurality of semiconductor device chips and stacking the plurality of chips so that the metal buried layers are in contact with each other.
該スクライブラインをまたいで、複数の貫通孔を形成し
、該貫通孔の内面に金属層を形成し、同時に、該金属層
と所望の電極・配線とを接続し、前記ウェーハを前記ス
クライブラインにそって切断して、内面に前記金属層を
有する凹部を周辺部に有する複数の半導体装置チップを
形成し、前記凹部に対応する領域に導電体棒を有するパ
ッケージ中に、前記チップの複数個を前記導電体棒と前
記凹部とが係合接触するように積層収納する工程を有す
る半導体装置の製造方法。(2) On the scribe line of the wafer for semiconductor devices,
A plurality of through holes are formed across the scribe line, a metal layer is formed on the inner surface of the through hole, and at the same time, the metal layer is connected to a desired electrode/wiring, and the wafer is placed on the scribe line. A plurality of semiconductor device chips are then cut along the edges to form a plurality of semiconductor device chips each having a concave portion at the periphery having the metal layer on the inner surface, and a plurality of the chips are placed in a package having a conductor bar in a region corresponding to the concave portion. A method for manufacturing a semiconductor device, comprising the step of stacking and storing the conductor rod and the recess so that they are in engagement contact with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59198361A JPS6177352A (en) | 1984-09-21 | 1984-09-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59198361A JPS6177352A (en) | 1984-09-21 | 1984-09-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6177352A true JPS6177352A (en) | 1986-04-19 |
Family
ID=16389827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59198361A Pending JPS6177352A (en) | 1984-09-21 | 1984-09-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6177352A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10321214A1 (en) * | 2003-05-12 | 2004-12-30 | Infineon Technologies Ag | Process for forming electrical contacts on a chip of a chip wafer for low cost radiofrequency identification chips brings contacts to the side faces of the chip |
| DE102006048583B3 (en) * | 2006-10-13 | 2008-01-31 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Component has two connections and four side surfaces with contact areas, where two side surfaces are opposite to each other, and contact areas of opposite side surfaces are connected with different connections |
| JP2010506426A (en) * | 2006-10-10 | 2010-02-25 | テッセラ，インコーポレイテッド | Edge connected wafer level laminate |
-
1984
- 1984-09-21 JP JP59198361A patent/JPS6177352A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10321214A1 (en) * | 2003-05-12 | 2004-12-30 | Infineon Technologies Ag | Process for forming electrical contacts on a chip of a chip wafer for low cost radiofrequency identification chips brings contacts to the side faces of the chip |
| JP2010506426A (en) * | 2006-10-10 | 2010-02-25 | テッセラ，インコーポレイテッド | Edge connected wafer level laminate |
| JP2013058763A (en) * | 2006-10-10 | 2013-03-28 | Tessera Inc | Edge connect wafer level stacking |
| DE102006048583B3 (en) * | 2006-10-13 | 2008-01-31 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Component has two connections and four side surfaces with contact areas, where two side surfaces are opposite to each other, and contact areas of opposite side surfaces are connected with different connections |
| US8331100B2 (en) | 2006-10-13 | 2012-12-11 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Device having several contact areas |
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