JPS6177329A - Thin film former - Google Patents

Thin film former

Info

Publication number
JPS6177329A
JPS6177329A JP19807184A JP19807184A JPS6177329A JP S6177329 A JPS6177329 A JP S6177329A JP 19807184 A JP19807184 A JP 19807184A JP 19807184 A JP19807184 A JP 19807184A JP S6177329 A JPS6177329 A JP S6177329A
Authority
JP
Japan
Prior art keywords
electrode
substrate
thin film
target
sputtering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19807184A
Other languages
Japanese (ja)
Inventor
Riyouichi Hazuki
巴月　良一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19807184A priority Critical patent/JPS6177329A/en
Publication of JPS6177329A publication Critical patent/JPS6177329A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Abstract

PURPOSE:To enable the formation of thin films by reducing the portion of electrons reaching the substrate and without damaging a solid where a thin film is to be formed on the surface, by a method wherein a contact electrode is provided between the target and the substrate, and a DC positive voltage is impressed on this control electrode. CONSTITUTION:This device is composed of the upper electrode 2 (cathode) and the lower electrode 3 (anode) of flat plate form arranged in a container 1 in opposition to each other, and of a contact electrode 4 made of an Mo line of mesh form arranged between these electrodes 2 and 3. The upper electrode 2 has a high frequency power source 6 which supplies high frequency power via matcher 5 and carriers a target material 7 (e.g. quartz glass) in the lower surface. The lower electrode 3 is usually grounded so as to mount a film-forming base 8 thereon. Further, the contact electrode 4 has a DC power source 9 and is supported by an insulating strut 10, so as to be situated between the base 8 mounted on the lower electrode and the upper electrode.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、薄膜形成装置に係り、特に、スパッタリング
法を利用した薄膜形成装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a thin film forming apparatus, and particularly relates to an improvement of a thin film forming apparatus using a sputtering method.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体ウェハ等の基板上に薄膜を形成する１つの方法と
して、スパッタリング法が用いられている。数十８７以
上の運動エネルギーを持つイオンビームを固体試料（タ
ーゲット）表面に照射したとき、固体表面近傍の試料原
子が入射イオンの持つエネルギーの一部を得て真空中に
放出されることになる。この放出された原子を基板上に
堆積することにより薄膜が形成される。A sputtering method is used as one method for forming a thin film on a substrate such as a semiconductor wafer. When the surface of a solid sample (target) is irradiated with an ion beam with a kinetic energy of tens of 87 or more, sample atoms near the solid surface gain part of the energy of the incident ions and are emitted into vacuum. . A thin film is formed by depositing the released atoms on a substrate.

しかしながら、この方法では、スパッタリング中にター
ゲット材料から放出される２次電子の影響により、膜の
堆積時に既に基板に形成されている素子の物性が劣化す
るという問題があった。However, this method has a problem in that the physical properties of elements already formed on the substrate during film deposition deteriorate due to the influence of secondary electrons emitted from the target material during sputtering.

特に、トランジスタおよび電極等の形成されたＭＯ８（
ｍｅｔａｌ　−ｏｘｉｄｅ　−ｓｅｍｊｃｏｎｄｕｃｔ
ｏｒ　）デバイスの表面に、スパッタリング法を用いて
酸化シリコン膜を形成するような場合、トランジスタの
しきい値電圧が変動してデバイスの信頼性が低下するこ
とになる。In particular, MO8(
metal-oxide-semjconduct
or) When a silicon oxide film is formed on the surface of a device by using a sputtering method, the threshold voltage of the transistor changes and the reliability of the device decreases.

こｈは、イオンビームがターゲットをスパッタする際に
、ターゲットから発生する２次電子が基板上に照射され
、下地であるＭＯＳデバイスのゲート酸化膜中に正電荷
、中性トラップ等の欠陥が生じるためであると考えられ
る。This is because when the ion beam sputters the target, secondary electrons generated from the target are irradiated onto the substrate, causing defects such as positive charges and neutral traps in the underlying gate oxide film of the MOS device. This is thought to be due to the

〔発明の目的〕[Purpose of the invention]

本発明は、前記実情に鑑みてなされたもので、スパッタ
リング法による薄膜の形成に際し、表面に薄膜を形成す
べき固体に損傷を与えることなく、薄膜形成を行なうこ
とのできるスパッタリング装置を提供することを目的と
する。The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a sputtering device that can form a thin film by sputtering without damaging the solid body on which the thin film is to be formed. With the goal.

〔発明の概要〕[Summary of the invention]

上記目的を達成するため、本発明では、ターゲットと基
板の間に制御電極を設け、ターゲットからの２次電子を
捕獲し、基板への電子による悪影響を大幅に低減するよ
うにしている。In order to achieve the above object, in the present invention, a control electrode is provided between the target and the substrate to capture secondary electrons from the target, thereby significantly reducing the adverse effect of the electrons on the substrate.

すなわち、本発明のスパッタリング装置では、ターゲッ
トと基板の間に制御筒、極を設け、この制御電極に直流
の正の電圧を印加することにより、ターゲットからの二
次電子をこの制御電極に導き、基板上に到達する電子を
低減している。That is, in the sputtering apparatus of the present invention, a control tube and a pole are provided between the target and the substrate, and by applying a positive DC voltage to the control electrode, secondary electrons from the target are guided to the control electrode. This reduces the number of electrons reaching the substrate.

〔発明の効果〕〔Effect of the invention〕

かかる構成によれば、スパッタリング中に生じる２次電
子は、制御電極に捕獲され、基板上まで到達し難くなり
、その結果、基板すなわち基板上に形成されている素子
への悪影響は大幅に抑制される。例えば、ＭＯＳデバイ
スのゲート酸化膜への影響は従来に比べて１０分の１以
下になる。According to this configuration, secondary electrons generated during sputtering are captured by the control electrode, making it difficult for them to reach the substrate, and as a result, the adverse effect on the substrate, that is, on the elements formed on the substrate, is significantly suppressed. Ru. For example, the influence on the gate oxide film of a MOS device is reduced to one-tenth or less compared to the conventional method.

〔実施例〕〔Example〕

以下、本発明の実施例について、図面を参照しつつ、詳
細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.

このスパッタリング装置は、図にその概略構成を示す断
面図を示す如く、容器１内に相対向して配置された平板
状の上部電極２（陰極）および下部電極３（陽極）と、
これらの電極２．３の間に配設された網目状のモリブデ
ン線からなる制御電極４とから構成されている。As shown in the cross-sectional view schematically showing the structure of the sputtering apparatus, this sputtering apparatus includes an upper electrode 2 (cathode) and a lower electrode 3 (anode) in the form of a flat plate, which are arranged opposite to each other in a container 1.
A control electrode 4 made of a mesh-like molybdenum wire is arranged between these electrodes 2.3.

該上部電極２は、整合器５を介して高層ｅ電力を供給す
る高周波電源６を具備すると共に、下面にターゲットｌ
料７（例えば石英ガラスＳｉｎ、）を担持している。The upper electrode 2 is equipped with a high frequency power source 6 that supplies high-rise e-power through a matching box 5, and has a target l on the lower surface.
A material 7 (for example, quartz glass Sin) is supported.

また、該下部電極３は、通常接地されており。Further, the lower electrode 3 is normally grounded.

この上に、膜形成用の基板８を載置するように構成され
ている（ここで該基板８とターゲット７との間隔は約８
３となっている。）。A substrate 8 for film formation is placed on top of this (here, the distance between the substrate 8 and the target 7 is approximately 8
It is 3. ).

更に、該制御電極４は、直流電源９を具備しており、絶
縁性の支柱１０により、下部電極上に載置さｔＩる膜形
成用の基板８と上部電極との間にくるように支持されて
いる。Furthermore, the control electrode 4 is equipped with a DC power source 9, and is supported by an insulating column 10 so as to be between the upper electrode and a substrate 8 for film formation placed on the lower electrode. has been done.

そして、容器ｌの両端にはガスを導入するためのガス導
入口１１とガスを排出するためのガス排出口１２とが相
対向して設けられている。A gas inlet 11 for introducing gas and a gas outlet 12 for discharging gas are provided at both ends of the container 1 to face each other.

次に、本発明実施例のスパッタリング装置を用いて、保
護膜としての酸化シリコン勝を形成する方法について説
明する。Next, a method for forming a silicon oxide film as a protective film using the sputtering apparatus of the embodiment of the present invention will be described.

ここで、膜形成用の基板８として、膀厚２００λのゲー
ト酸化膜を有するＭＯＳ　）ランジスタおよび電極の作
り込まれたシリコン基板をまず、下部電極３上の所定の
位置に載置する。Here, as the substrate 8 for film formation, a silicon substrate having a gate oxide film having a thickness of 200λ and a MOS transistor and an electrode formed therein is first placed at a predetermined position on the lower electrode 3.

そして、容器１内をＩ　ＸＩＯ（Ｔｏｒｒ）程度の真空
に排気した後、ガス導入口１１よりアルゴン（Ａｒ　）
ガスを導入し、容器１内のガス圧を１０ｍＴｏｒｒに保
持する。After evacuating the inside of the container 1 to a vacuum of about IXIO (Torr), argon (Ar)
Gas is introduced and the gas pressure inside the container 1 is maintained at 10 mTorr.

次いで、制御電極４を＋５０Ｖに維持すると共に高周波
電源６をＯＮにし、５Ｗ／ｌＷ１”の高周波電力を印加
することにより、上部電極２と下部電極３との間で放電
を起し、アルゴンイオンによりターゲット材料７をスパ
ッタリングすることにより、基板８０表面に酸化シリコ
ン勝を約１μｍ堆積させる。Next, by maintaining the control electrode 4 at +50V and turning on the high frequency power supply 6 to apply a high frequency power of 5W/lW1'', a discharge is caused between the upper electrode 2 and the lower electrode 3, and argon ions are generated. By sputtering the target material 7, about 1 μm of silicon oxide is deposited on the surface of the substrate 80.

このようにして酸化シリコン膜を形成した後、スパッタ
リング装置から該基板をとり出してフォトリソエツチン
グにより電極用開口部を穿孔し。After forming the silicon oxide film in this manner, the substrate was taken out from the sputtering apparatus and an opening for an electrode was formed by photolithography.

更に４５０℃のフォーミングガス中で約２０分間にわた
る熱処理を行なった。Furthermore, heat treatment was performed for about 20 minutes in a forming gas at 450°C.

熱処理後の該基板内のＭＯＳトランジスタのしきい値電
圧Ｖｔｈを測定した結果、本発明のスパッタリング装置
による該酸化シリコン膜形成前に比べて５ｍＶ変動した
に過ぎなかった。As a result of measuring the threshold voltage Vth of the MOS transistor in the substrate after the heat treatment, it was found that it varied by only 5 mV compared to before the silicon oxide film was formed using the sputtering apparatus of the present invention.

比較のために、制御電極を具備していない従来のスパッ
タリング装置によって上記と同一のスパッタ条件で酸化
シリコン膜を形成した場合のＭＯＳトランジスタのしき
い値電圧Ｖｔｈ株１１定すると、形成前に比べて１００
ｍＶも変動したことがわかった。For comparison, when a silicon oxide film is formed using a conventional sputtering apparatus without a control electrode under the same sputtering conditions as above, the threshold voltage Vth of a MOS transistor is compared to that before formation. 100
It was found that mV also varied.

これらの比較から明らかなように、本発明実施例のスパ
ッタリング装置の使用により、しきい値電圧の変動は２
０分の１になっている。As is clear from these comparisons, by using the sputtering apparatus of the embodiment of the present invention, the fluctuation in threshold voltage is reduced by 2.
It has become 1/0.

なお、制御電極を構成する材料としては、実施例に示し
たモリブデン（Ｍｏ）に限定されるものではなく、タン
グステン（Ｗ）等高融点金属であればよい。Note that the material constituting the control electrode is not limited to molybdenum (Mo) shown in the embodiment, but may be any high melting point metal such as tungsten (W).

また、スパッタガスについても、アルゴンに限定される
ことなく、ヘリウム（Ｈｅ）、ネオン（Ｎｅ）、クリプ
トン（Ｋｒ）、キセノン（Ｘｅ）等、他のガスを用いる
場合にも、同様の効果が奏効さｆする。Furthermore, the sputtering gas is not limited to argon, and similar effects can be obtained when using other gases such as helium (He), neon (Ne), krypton (Kr), and xenon (Xe). I'm going to f.

更に、ターゲット材料を担持する上部電極上にマグネッ
トを配設してなるマグネトロンスパッタあるいは、基楓
側の下部電極にも電力を印加するバイアススパッタ等に
おいても１本発明は有効である。Furthermore, the present invention is also effective in magnetron sputtering in which a magnet is disposed on the upper electrode supporting the target material, bias sputtering in which power is also applied to the lower electrode on the base maple side, and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

図は、本発明実施例のスパッタリング装置の概略構成を
示す断面図である。 １・・・容器、２・・・上部電極、３・・・下部筒、極
、４・・・制御電極、５・・・整合器、６・・・高周波
電源、７・・・ターゲット材料、８・・・基板、９・・
・直流電源、１０・・・支柱、１１・・・ガス導入口、
１２・・・ガス排出口。 手続補正書 １、事件の表示 昭和５９年特許願第１９８０７１号 ２、発明の名称 薄膜形成装置 ３、補正をする者 事件との関係　　特許出願人 （３０７）　　株式合着　東芝 ４、代理人 （〒１０４）東京都中央区銀座２丁目１１番２号明細皇
の特許請求の笥凹の欄、発明の詳細な説明の欄、および
図面 ６、補正の内容 別紙の通り ６、補正の内容 （１１本願の明細書中、特許請求の範囲を別紙の如く補
正する。 （２）　　回申、第２ページ第８行目および第３ページ
第３行目の「ビーム」を削除する。 （３）回申、第７ページ第１３行目乃至第１４行目の「
高融点金属であればよい。」を「高融点金属あるいはス
テンレスであってもよい。」と補正する。 （４）本願の明細書に添付した図面を別紙の如く補正す
る。 別紙 ２、特許請求の範囲 ターゲット材料をスパッタリングし、他方の電極上の基
板表面上に薄膜を堆積するようにした薄膜形成装置にお
いて、前記ターゲット材料と前記基板との間に相当する
位置に制御電極を具備したことを特徴とする薄膜形成装
置。 （２）前記制御電極は網目状構造をとると共に、直流電
圧が印加されるように構成されていることを特徴とする
特許請求の範囲第（１）項記載の薄膜形成装置。The figure is a sectional view showing a schematic configuration of a sputtering apparatus according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Container, 2... Upper electrode, 3... Lower cylinder, pole, 4... Control electrode, 5... Matching device, 6... High frequency power supply, 7... Target material, 8... Board, 9...
・DC power supply, 10... Support, 11... Gas inlet,
12...Gas exhaust port. Written amendment 1, Indication of the case 1980 Patent Application No. 198071 2, Name of the invention Thin film forming device 3, Person making the amendment Relationship with the case Patent applicant (307) Stock merger Toshiba 4, Agent (〒 104) 2-11-2 Ginza, Chuo-ku, Tokyo In the specification, the claims are amended as shown in the attached sheet. (2) "Beam" is deleted from the eighth line of the second page and the third line of the third page of the circular. (3) The circular is deleted from the eighth line of the second page and the third line of the third page. , page 7, lines 13 and 14, “
Any metal with a high melting point may be used. " should be corrected to "It may be made of high melting point metal or stainless steel." (4) The drawings attached to the specification of this application shall be amended as shown in the attached sheet. Attachment 2, Claims In a thin film forming apparatus for sputtering a target material and depositing a thin film on the surface of a substrate on the other electrode, a control electrode is located at a position corresponding to between the target material and the substrate. A thin film forming apparatus characterized by comprising: (2) The thin film forming apparatus according to claim (1), wherein the control electrode has a mesh structure and is configured to be applied with a DC voltage.

Claims (2)

【特許請求の範囲】[Claims] （１）高エネルギーを有するイオンビームにより、互い
に対向した電極のうち一方の電極上のターゲット材料を
スパッタリングし、他方の電極上の基板表面上に薄膜を
堆積するようにした薄膜形成装置において、前記ターゲ
ット材料と前記基板との間に相当する位置に制御電極を
具備したことを特徴とする薄膜形成装置。(1) A thin film forming apparatus in which a target material on one of mutually opposing electrodes is sputtered using an ion beam having high energy, and a thin film is deposited on the substrate surface on the other electrode. A thin film forming apparatus characterized in that a control electrode is provided at a position corresponding to between a target material and the substrate. （２）前記制御電極は網目状構造をとると共に、直流電
圧が印加されるように構成されていることを特徴とする
特許請求の範囲第（１）項記載の薄膜形成装置。(2) The thin film forming apparatus according to claim (1), wherein the control electrode has a mesh structure and is configured to be applied with a DC voltage.
JP19807184A 1984-09-21 1984-09-21 Thin film former Pending JPS6177329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19807184A JPS6177329A (en) 1984-09-21 1984-09-21 Thin film former

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19807184A JPS6177329A (en) 1984-09-21 1984-09-21 Thin film former

Publications (1)

Publication Number Publication Date
JPS6177329A true JPS6177329A (en) 1986-04-19

Family

ID=16385036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19807184A Pending JPS6177329A (en) 1984-09-21 1984-09-21 Thin film former

Country Status (1)

Country Link
JP (1) JPS6177329A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193172A (en) * 1987-10-05 1989-04-12 Matsushita Electric Ind Co Ltd Thin-film transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193172A (en) * 1987-10-05 1989-04-12 Matsushita Electric Ind Co Ltd Thin-film transistor

Similar Documents

Publication Publication Date Title
US3879746A (en) Gate metallization structure
US3474021A (en) Method of forming openings using sequential sputtering and chemical etching
US6224724B1 (en) Physical vapor processing of a surface with non-uniformity compensation
US3617463A (en) Apparatus and method for sputter etching
JPH10330938A (en) Ionization sputtering device and ionization sputtering method
JPS6177329A (en) Thin film former
JP4164154B2 (en) Ionization sputtering equipment
JPS61174725A (en) Thin film forming apparatus
JPS60228675A (en) Method for depositing tungsten
KR100303632B1 (en) Cold cathode element
JPS61180441A (en) Thin-film forming device
JPS61292321A (en) Electron beam transfer equipment
JPS6348933Y2 (en)
JPH02148722A (en) Manufacture of semiconductor integrated circuit device
JPH04314864A (en) Method for plasma-cleaning substrate surface
JPH01149474A (en) Manufacture of thin film transistor
JP2008051639A (en) Secondary ion mass analysis method for insulating material
JPS54100988A (en) Ion plating device
JPH05295522A (en) Formation of thin film
JPS5822381A (en) Method and apparatus for plasma etching
JPS61198636A (en) Thin film former
JP2001244100A (en) Plasma processing apparatus
JPS60190560A (en) Deposition method of molybdenum
JPH06306578A (en) Method and device for forming electromagnetic shielding film
JPS61168962A (en) Manufacture of thin-film transistor