JPS617662A - Solid-state image pickup element - Google Patents

Solid-state image pickup element

Info

Publication number
JPS617662A
JPS617662A JP59129463A JP12946384A JPS617662A JP S617662 A JPS617662 A JP S617662A JP 59129463 A JP59129463 A JP 59129463A JP 12946384 A JP12946384 A JP 12946384A JP S617662 A JPS617662 A JP S617662A
Authority
JP
Japan
Prior art keywords
electrodes
region
ccd
solid
schottky junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59129463A
Other languages
Japanese (ja)
Other versions
JPH0658952B2 (en
Inventor
Naoki Yuya
直毅 油谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59129463A priority Critical patent/JPH0658952B2/en
Publication of JPS617662A publication Critical patent/JPS617662A/en
Publication of JPH0658952B2 publication Critical patent/JPH0658952B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/148Charge coupled imagers

Abstract

PURPOSE:To obtain a solid-state image pickup element having a large numerical aperture by utilizing a Schottky junction electrode formed onto a region, in which charges are stored and transferred, as an electrode for a CCD and enabling optical detection and the transfer of charges. CONSTITUTION:When electrodes 181-184 having Schottky junctions and gate electrodes 171-174 are biassed at the same voltage, potential to holes in a P type region 162 in the lower sections of the electrodes 171-174 is made lower than that in the lower sections of the electrodes 181-184. When infrared rays are projected under the state in which potential in the region 162 under the electrodes 182, 184 is biassed so as to be made lower than potential in the region 162 under the electrodes 171, 173, electron-hole pairs are generated in the electrodes 181-184. Holes having energy exceeding the barriers of Schottky junctions among the electron-hole pairs are injected to the region 162. When driving pulses deflected to negative number from 0V, phase thereof is displaced at 180 deg., are each transmitted over conductors phiA1, phiA2, optical signal charges collected to sections except the electrodes 172, 174 are transferred in the right direction. According to the constitution, an image pickup element having a large numerical aperture is obtained.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、光に対し感度をもつショットキ接合の金J
I4III電極を電荷結合素子(以下CCDという)の
転送電極として利用した固体撮像素子に関するものであ
る。
[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a Schottky bonded gold J that is sensitive to light.
The present invention relates to a solid-state imaging device using an I4III electrode as a transfer electrode of a charge-coupled device (hereinafter referred to as a CCD).

〔従来技術〕[Prior art]

光検出系子7レイと電荷転送素子を同一あ半導体基板上
に形成した固体撮像素子を撮像装置に使用すると小型、
軽量、低消費電力、かつ高信頼性の撮像装置が実現でき
る。
When a solid-state imaging device in which a photodetection system 7 ray and a charge transfer device are formed on the same semiconductor substrate is used in an imaging device, it can be made compact,
A lightweight, low power consumption, and highly reliable imaging device can be realized.

可視領域の撮像においては、最近ではシリコン集積回路
技術の発展に伴ない撮像用電子管差みの解像力を備えた
固体撮像素子が開発されている。
In the field of imaging in the visible region, solid-state imaging devices having the resolving power of an imaging electron tube have recently been developed with the development of silicon integrated circuit technology.

一方、赤外線撮像装置は物体の熱像なとらえることがで
きるので、環境監視、°暗視監視、資源探索。
On the other hand, infrared imaging devices can capture thermal images of objects, so they are useful for environmental monitoring, night vision monitoring, and resource exploration.

温度分布観測等多方面の分野で使用されている。It is used in many fields such as temperature distribution observation.

ところが、現在実用化されている赤外線撮像装置の多く
は、単一の赤外線検出器を使い、機械的走査により熱像
を撮像している。そのため近年、赤外領域においても固
体撮像素子の開発が精力的に進められている11+#に
シリコンショットキ接合な赤外線検出部とした赤外線固
体撮像素子においては、実用に酎えられる画素数を持っ
たものが開発されつ瓦ある。
However, most infrared imaging devices currently in practical use use a single infrared detector to capture thermal images through mechanical scanning. Therefore, in recent years, the development of solid-state image sensors in the infrared region has been vigorously promoted. Things are still being developed.

従来の赤外線固体撮像素子として第1図に示すものがあ
る。
A conventional infrared solid-state imaging device is shown in FIG.

第1図において、1はショットキ接合を用いた赤外光検
出部、2,3はそれぞれCODよりなる垂直シフトレジ
スタ、水平シフトレジスタであり、4は前記赤外光検出
部1から前記シフトレジスタ2へ光信号を移すトランス
ファーゲート、5は電荷検出部である。
In FIG. 1, 1 is an infrared light detection section using a Schottky junction, 2 and 3 are a vertical shift register and a horizontal shift register made of COD, respectively, and 4 is from the infrared light detection section 1 to the shift register 2. 5 is a charge detection section.

第2図は第1図のA−A線における断面図であるO 第2図にセいて、6はp型シリコン基板、1はこのp型
シリコン基板6の上に金、パラジウム。
FIG. 2 is a cross-sectional view taken along the line A--A in FIG.

白金硅化物、パラジウム硅化物、イリジウム硅化物など
の金属または金属硅化物を蒸着し【形成した赤外光検出
部1のショットキ接合の金属側電極、8はこの金属側電
極7の周囲のn−領域であるガードリング、9は前記ト
ランスファーゲート4のゲート電極、10は前記金属側
電極7の一部に重なるn 領域、11.12は前記垂直
シフトレジスタ2のCCDのゲート電極と、n型埋込み
チャネル、13は素子分離と絶縁用の酸化硅素膜、14
は素子保護用の酸化硅素膜、14は素子保護用の窒化硅
素膜である。
The metal side electrode of the Schottky junction of the infrared light detecting section 1 is formed by vapor-depositing metal or metal silicide such as platinum silicide, palladium silicide, iridium silicide, etc. 8 is the n- side electrode around this metal side electrode 7. A guard ring 9 is a gate electrode of the transfer gate 4, an n-type region 10 overlaps a part of the metal side electrode 7, and 11.12 is a gate electrode of the CCD of the vertical shift register 2 and an n-type buried region. Channel, 13 is a silicon oxide film for element isolation and insulation, 14
14 is a silicon oxide film for protecting the device, and 14 is a silicon nitride film for protecting the device.

次に動作について説明する。Next, the operation will be explained.

赤外光検出部1へ入射した赤外光によって、ショットキ
接合の金属側電極T中に電子・正孔対が生成される。こ
の正孔のうち、ショットキ障壁の高さを越えるエネルギ
ーを持つものは、p型シリコン基板6に注入され、ショ
ットキ接合に光信号電荷が蓄積される。赤外光検出部1
の検出可能な最大波長はショットキ障壁の高さによって
決まる。
The infrared light incident on the infrared light detection section 1 generates electron-hole pairs in the metal side electrode T of the Schottky junction. Among these holes, those with energy exceeding the height of the Schottky barrier are injected into the p-type silicon substrate 6, and optical signal charges are accumulated in the Schottky junction. Infrared light detection section 1
The maximum detectable wavelength of is determined by the height of the Schottky barrier.

たとえば金属側電極7にPtSiを使うと、PtSiと
p型Stのショットキ障壁の高さは0.25evである
ので、0.−25ev以上のエネルギーを持った光(波
長5μm以下の光ンが検出できる。このようにして赤外
光検出部1のショットキ接合に蓄積された光信号電荷は
トランスファーゲート4を開くことくより垂直シフトレ
ジスタ2のCCDのn型埋込みチャネル12に移される
。光信号電荷が垂直シフトレジスタ2へ移された後、ト
ランスファーゲート4が閉じられ、赤外光検出部1には
次の周期の光信号電荷が蓄積される。一方、垂直シフト
レジスタ2に移された光信号電荷はCCDのn型埋込み
チャネル12の中を垂直方向へ転送され、各垂直シフト
レジスタ2の1水平ライン毎に水平シフトレジスタ3へ
送られた水平方向に転送されて電荷検出部5から映像信
号として外部に取り出される。
For example, if PtSi is used for the metal side electrode 7, the height of the Schottky barrier between PtSi and p-type St is 0.25ev, so 0. Light with an energy of −25 ev or more (photon with a wavelength of 5 μm or less can be detected). The optical signal charge is transferred to the n-type buried channel 12 of the CCD of the shift register 2. After the optical signal charge is transferred to the vertical shift register 2, the transfer gate 4 is closed, and the infrared light detector 1 receives the optical signal of the next period. On the other hand, the optical signal charge transferred to the vertical shift register 2 is transferred vertically in the n-type buried channel 12 of the CCD, and is transferred to the horizontal shift register for every horizontal line of each vertical shift register 2. 3, the signal is transferred in the horizontal direction and taken out from the charge detection section 5 as a video signal.

このようにして赤外光検出部1の各画素への赤外光の入
射光量に対応した映像信号が得られる。
In this way, a video signal corresponding to the amount of infrared light incident on each pixel of the infrared light detection section 1 is obtained.

従来の赤外線固体撮像素子は以上のように構成されてい
るので、水平方向においては、赤外光検出部1の各画素
の間にトランスファーゲート4と垂直シフトレジスタ2
が存在するため開口率(撮像領域の面積に対する有効感
光部の面積の割合)が小さかった。赤外光検出部1と垂
直シフトレジスタ20面積比は赤外光検出部1のショッ
トキ接合が蓄積できる光信号電荷量と垂直シフトレジス
タ2のCCDが転送できる最大電荷転送量できまるため
、極端に赤外光検出部10面積を大きくすることはでき
ないという欠点があった。そのため従来の赤外線固体撮
像素子では赤外光検出部1を大きくして開口率を大きく
することKは限界があった。
Since the conventional infrared solid-state image sensor is configured as described above, in the horizontal direction, a transfer gate 4 and a vertical shift register 2 are provided between each pixel of the infrared light detection section 1.
Because of this, the aperture ratio (the ratio of the area of the effective photosensitive area to the area of the imaging region) was small. The area ratio between the infrared light detection section 1 and the vertical shift register 20 is determined by the amount of optical signal charge that can be accumulated by the Schottky junction of the infrared light detection section 1 and the maximum charge transfer amount that can be transferred by the CCD of the vertical shift register 2. There was a drawback that the area of the infrared light detection section 10 could not be increased. Therefore, in the conventional infrared solid-state imaging device, there is a limit to increasing the aperture ratio by increasing the size of the infrared light detection section 1.

〔発明の概要〕[Summary of the invention]

この発明は、上述のような従来のものの欠点を除去する
ためになされたもので、垂直シフトレジスタのCODの
電極の一部をショットキ接合の金属側電極にしてCCD
に赤外光検出機能を持たせ、垂直シフトレジスタで光検
出ができるようにすることにより開口率の大きな赤外線
用の固体撮像素子を提供するものである。以下、この発
明の一実施例を図面について説明する。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and a part of the electrode of the COD of the vertical shift register is used as the metal side electrode of the Schottky junction.
The present invention provides an infrared solid-state image pickup device with a large aperture ratio by providing an infrared light detection function and enabling light detection using a vertical shift register. An embodiment of the present invention will be described below with reference to the drawings.

〔発明の実施例〕[Embodiments of the invention]

第3図、第4図はこの発明の一実施例を示す要部の平面
図と断面図である。
FIGS. 3 and 4 are a plan view and a sectional view of essential parts showing an embodiment of the present invention.

第3図において、15はn型シリコン基板、161゜1
62.163,164は前記n型シリコン基板15の表
面領域に形成されたp型領域で、CCDのp型埋込みチ
ャネルになる。171,172゜173.174は水平
方向は電気的につながり、前記p型領域161〜164
0表面に絶縁膜を挾んで形成されたCCDのゲート電極
、181,182゜183.184は水平方向は電気的
につながり、垂直方向は前記ゲート電極171〜174
と交互に配列形成され、互いに絶縁されて前記p型領域
161〜164の表面とショットキ接合を形成するショ
ットキ接合の電極である。φ48.φA2は前記ゲート
電極111〜174と前記ショットキ接合の電極181
〜184に接続されたCCDの駆動パルス(同時にこれ
が印加される導線を表わすものとする)である。
In Fig. 3, 15 is an n-type silicon substrate, 161°1
62, 163 and 164 are p-type regions formed in the surface region of the n-type silicon substrate 15, which become p-type buried channels of the CCD. 171, 172° 173, 174 are electrically connected in the horizontal direction, and the p-type regions 161 to 164
Gate electrodes 181, 182, 183, and 184 of the CCD formed on the 0 surface with an insulating film sandwiched therebetween are electrically connected in the horizontal direction, and are electrically connected to the gate electrodes 171 to 174 in the vertical direction.
Schottky junction electrodes are arranged alternately and insulated from each other to form a Schottky junction with the surfaces of the p-type regions 161 to 164. φ48. φA2 is the gate electrode 111 to 174 and the Schottky junction electrode 181.
.about.184 (assuming that it represents the conductor to which it is applied at the same time).

第4図は第3図のX−X線における断面図で、191.
192,193,194はそれぞれ前記ゲート電極17
1〜174と前記ショットキ接合の電極181〜184
の間の絶縁をする絶縁膜である。
FIG. 4 is a cross-sectional view taken along line X-X in FIG. 3, and shows 191.
192, 193, and 194 are the gate electrodes 17, respectively.
1 to 174 and the Schottky junction electrodes 181 to 184
This is an insulating film that provides insulation between the two.

次に動作について説明する。Next, the operation will be explained.

第4図において、導線φAlを0vVC導線φ、2を負
にバイアスしたときのp副領域162での正孔に対する
電位分布を破線で示して′ある。
In FIG. 4, the potential distribution for holes in the p sub-region 162 is shown by a broken line when the conducting wire φAl is biased to 0vVC and the conducting wire φ,2 is negatively biased.

ショットキ接合の電極181〜184とゲート電極17
1〜174を同電圧にバイアスした場合、これら両電極
の下のp副領域162の正孔に対する電位は、ゲート電
極111〜174の下の方が、ショットキ接合の電極1
81〜184の下よりも低くなる。そこでショットキ接
合の電極182゜184の下のp副領域162の電位が
導線φ4.によってOvにバイアスされたゲート電極1
11゜173の下のp副領域162の電位より低くなる
よ5に導線φ、2を負にバイアスするとp副領域162
の正孔に対する電位分布は第4図の破線で示したように
なる。
Schottky junction electrodes 181 to 184 and gate electrode 17
1 to 174 are biased to the same voltage, the potential for holes in the p sub-region 162 under these two electrodes is higher than that of the Schottky junction electrode 1 under the gate electrodes 111 to 174.
It is lower than 81-184. Therefore, the potential of the p sub-region 162 under the Schottky junction electrode 182°184 is changed to the conductive wire φ4. Gate electrode 1 biased to Ov by
11° 173 so that the potential is lower than the potential of the p sub-region 162 under the conductor φ, 2 is biased negatively, the p sub-region 162
The potential distribution for holes is as shown by the broken line in FIG.

この状態で赤外線が入射すると、ショットキ接合の電極
181〜184内忙電子・正孔対が生成される。この正
孔のうちショットキ接合の障壁φmsを越えるエネルギ
ーを持つものはp副領域162に注入される。たとえば
、ショットキ接合の電極181〜184の材料として白
金硅化物PtSiを使用すると、φmm =0.25 
eVになり、最大5μmまでの波長の赤外線に対し入射
光量に応じた正孔の信号電荷が注入される。p副領域1
62に注入された正孔は一番電位の低いゲート電極17
2゜174の下に集められ、光信号電荷として蓄積され
る。呈温においてはφms =Q、25 eV程度の低
いショットキ障壁では熱生成キャリアが多いため光信号
電荷の蓄積はできないが、赤外線固体撮像素子は一般に
液体窒素温度77に以下の低温で動作させるので熱生成
キャリアの発生を充分小さくできるため、元信号電荷の
蓄積が可能になる。
When infrared rays are incident in this state, busy electron/hole pairs are generated within the Schottky junction electrodes 181 to 184. Of these holes, those with energy exceeding the Schottky junction barrier φms are injected into the p sub-region 162. For example, if platinum silicide PtSi is used as the material for the Schottky junction electrodes 181 to 184, φmm = 0.25
eV, and a hole signal charge corresponding to the amount of incident light is injected into infrared rays having a wavelength of up to 5 μm. p subregion 1
The holes injected into the gate electrode 17 have the lowest potential.
2°174 and accumulated as optical signal charges. At temperature, φms = Q, and at a Schottky barrier as low as 25 eV, there are many thermally generated carriers, so optical signal charges cannot be accumulated.However, infrared solid-state imaging devices are generally operated at a low temperature below the liquid nitrogen temperature of 77, Since the generation of generated carriers can be sufficiently reduced, it becomes possible to accumulate original signal charges.

光信号電荷を一定時間蓄積した後、導線φ、1゜φAt
Kそれぞれ互に180°位相のずれたOvから負に振れ
る駆動パルスφAI+φ、、を与えると、ゲート電極I
T2.174の下に集められた光信号電荷は第4図の図
中右方向へ転送さ匁る。転送できる最大電荷転送量はゲ
ート電極111〜174の下のp型領域161〜164
に蓄えられる電荷量によつ【きまる。
After accumulating the optical signal charge for a certain period of time, the conductor φ, 1゜φAt
When driving pulses φAI+φ, which swing negatively from Ov, which are 180° out of phase with each other, are applied to the gate electrode I
The optical signal charges collected under T2.174 are transferred to the right in the diagram of FIG. The maximum charge transfer amount that can be transferred is
Depends on the amount of charge stored in.

次にこの発明の主要部の製造方法の一実施例を第5図を
用いて説明する。
Next, an embodiment of a method for manufacturing the main part of the present invention will be described with reference to FIG.

第5図において、n型シリコン基板15の上にp副領域
162<161,163,164についても同じ)をエ
ピタキシャル成長もしくはイオン注入により形成し、p
型領域16″2の表面を薄く酸化してゲート酸化硅素膜
20を形成し、ポリシリコンによりゲート電極111〜
174を形成する。その後、酸化硅素膜20をCVD法
により積層すると、第5図(a)の形状になる。次に酸
化硅素膜20を異方性エツチングによりポリシリコンの
ゲート電極171〜1140両横の酸化硅素膜201.
202,203.204の部分を残してエツチングする
と第5図(b)のような状態になる。
In FIG. 5, p sub-regions 162<161, 163, 164) are formed on an n-type silicon substrate 15 by epitaxial growth or ion implantation, and
The surface of the mold region 16''2 is thinly oxidized to form a gate silicon oxide film 20, and the gate electrodes 111 to 111 are made of polysilicon.
174 is formed. Thereafter, a silicon oxide film 20 is laminated by the CVD method, resulting in the shape shown in FIG. 5(a). Next, the silicon oxide film 20 is anisotropically etched to form a silicon oxide film 201 on both sides of the polysilicon gate electrodes 171 to 1140.
If the etching is performed while leaving the portions 202, 203, and 204, the result will be as shown in FIG. 5(b).

その上に白金またはイリジウムまたはパラジウム等の金
属を蒸着し熱処理により金属硅化*を形成するとショッ
トキ接合の電極181〜184が第5図(C)に示すよ
うに自己整合で形成される。また、ポリシリコンの上に
も金属硅化物が形成されるのでポリシリコンの配線抵抗
か下る。
When a metal such as platinum, iridium, or palladium is vapor-deposited thereon and metal silicide* is formed by heat treatment, Schottky junction electrodes 181 to 184 are formed in a self-aligned manner as shown in FIG. 5(C). Further, since metal silicide is also formed on the polysilicon, the wiring resistance of the polysilicon decreases.

次に、この発明の固体撮像素子の全体の構成の一実施例
を第6図について説明する。
Next, an embodiment of the overall configuration of the solid-state image sensing device of the present invention will be described with reference to FIG.

第6図において、21は第3図、第4図に示した構造の
感光部のCOD、22は蓄積部のCCD。
In FIG. 6, 21 is the COD of the photosensitive section having the structure shown in FIGS. 3 and 4, and 22 is the CCD of the storage section.

φ11.φ43.とφcIとφc2はそれぞれ前記蓄積
部のCCD22と水平読出し部の水平シフトレジスタ3
のCCDの2相駆動ンくルス(同時に導線をも表わす)
である。感光部のCCD21は赤外線を検出しなければ
ならないので第3図、第4図に示した構造のCCDにす
るが、蓄積部のCCD22と水平読出部の水平゛シフト
レジスタ3は半導体表面に絶縁膜を挾んで電極を形成す
る通常よく使われるCODで構成してもよ〜・。
φ11. φ43. , φcI and φc2 are the CCD 22 of the storage section and the horizontal shift register 3 of the horizontal readout section, respectively.
Two-phase drive circuit of CCD (also represents the conductor)
It is. Since the CCD 21 in the photosensitive section must detect infrared rays, the CCD has the structure shown in FIGS. It can also be constructed using COD, which is commonly used and which forms electrodes by sandwiching them.

次に動作について説明する@ 撮像する物体の光像は感光部のCCD21上に結像され
る。感光部のCCD21において、導線φ、1をQVK
、導線φA2を負にバイアスし、第4図で述べた原理で
光信号電荷を一定時間蓄積した後、導線φ、8.φ、、
と導線φ38.φ□に2相駆動パルスを与え、感光部の
CCD21と蓄積部のCCD22を動作させて感光部の
C0D21 K蓄積されていた一画面分の光信号電荷を
蓄積部のCCD22に転送する。光信号電荷を転送して
いる間も光は入射してくるので、この転送は光信号電荷
蓄積時間圧対し充分早いことが望ましい。また、蓄積部
のCCD22は感光部(’)CCD21に蓄積されてい
た一画面分の光信号を一時蓄積するので、蓄積部のCC
D22は感光部のCCD21と同数もしくはそれ以上の
電極数を持っていなくてはならない。蓄積部のCCD2
2への転送が完了すると今度は導線φ、7.φ、2とφ
C1l φc2にそれぞれ2相駆動パルスを与え、蓄積
部のCCD22と水平読出し部の水平シフトレジスタ3
を動作させて蓄積部のCCD22に蓄積されていた一画
面分の光信号電荷な一水平ライン毎に読出す。この間に
感光部のCCD21 Kは次の周期の光信号が蓄積され
る。
Next, the operation will be explained.@ The optical image of the object to be imaged is formed on the CCD 21 of the photosensitive section. In the CCD 21 of the photosensitive section, connect the conductor φ,1 to QVK.
, conductive wire φA2 is negatively biased, and after accumulating optical signal charges for a certain period of time according to the principle described in FIG. 4, conductive wires φ, 8. φ,,
and conductor wire φ38. A two-phase drive pulse is applied to φ□, the CCD 21 of the photosensitive section and the CCD 22 of the storage section are operated, and the optical signal charge for one screen that has been accumulated in the C0D21K of the photosensitive section is transferred to the CCD 22 of the storage section. Since light is incident even while the optical signal charges are being transferred, it is desirable that this transfer is sufficiently fast compared to the optical signal charge accumulation time. In addition, since the CCD 22 of the storage section temporarily stores the optical signal for one screen that was stored in the photosensitive section (') CCD 21, the CCD 22 of the storage section
D22 must have the same number of electrodes as or more than the number of electrodes of CCD21 in the photosensitive section. CCD2 in storage section
When the transfer to 2 is completed, the conductor φ, 7. φ, 2 and φ
A two-phase driving pulse is applied to C1l and φc2, respectively, and the CCD 22 of the storage section and the horizontal shift register 3 of the horizontal readout section are
is operated to read out one screen's worth of optical signal charges stored in the CCD 22 of the storage section for each horizontal line. During this time, the CCD 21K of the photosensitive section accumulates the optical signal of the next cycle.

このようにして感光部のCCD21に結像された光像に
応じた画像信号が続出される。
In this way, image signals corresponding to the light images formed on the CCD 21 of the photosensitive section are successively output.

また、光信号蓄積期間に導線φ、0.φA2に加えるバ
イアスを、φA1をOvに、φ、、を負にバイアスした
周期の次の周期はφ、1を負に、φA2をOvKバイア
スして1周期ごとに光信号を蓄積する領域をずらし2周
期で1画面を構成する動作をさせると垂直方向の解像度
を上げることができる。
Also, during the optical signal accumulation period, the conducting wire φ, 0. The bias applied to φA2 is set such that φA1 is set to Ov, φ, , is biased negatively, and in the next cycle, φ,1 is set to negative, and φA2 is biased to OvK, and the area where the optical signal is accumulated is shifted every cycle. Vertical resolution can be increased by performing an operation that configures one screen in two cycles.

なお、上記実施例では蓄積部のCCD22と水平シフト
レジスタ3の2相駆動の場合について述べたが、信号電
荷の蓄積と転送が可能であれば他の種類の駆動方式のC
CDを使用してもよい。
In the above embodiment, the CCD 22 in the storage section and the horizontal shift register 3 are driven in two phases, but other types of driving methods may be used as long as the accumulation and transfer of signal charges is possible.
A CD may also be used.

また、感光部のCCD21は第4図に示した2相駆動の
場合について述べたが、他の種類の駆動方法をとること
も可能である。
Although the CCD 21 of the photosensitive section is driven in two phases as shown in FIG. 4, other types of driving methods are also possible.

第7図に感光部のCCD21の他の駆動方法の一実施例
を示す。
FIG. 7 shows an embodiment of another method for driving the CCD 21 of the photosensitive section.

第7図において、ゲート電極111〜174とショット
キ接合の電極181〜184の下のp属領域162の電
位は電極に印加している電圧が同じならばゲート電極1
71〜174の下の方が低くなる。。そこで、ショット
キ接合の電極181〜184とゲート電極171〜11
4に電圧の異なる駆動パルスを印加して、それぞれの駆
動パルスのハイレベルとローレベルにおいてショットキ
接合の電極181〜184とゲート電極111〜174
の下のp属領域162の電位が同じになるようにする。
In FIG. 7, if the voltages applied to the gate electrodes 111-174 and the Schottky junction electrodes 181-184 are the same, the potential of the p-type region 162 under the gate electrodes 111-174 and Schottky junction electrodes 181-184 is
The lower part of 71-174 is lower. . Therefore, the Schottky junction electrodes 181 to 184 and the gate electrodes 171 to 11
Driving pulses with different voltages are applied to Schottky junction electrodes 181 to 184 and gate electrodes 111 to 174 at high and low levels of the respective driving pulses.
The potentials of the p-type region 162 under the p-type region 162 are made to be the same.

すなわち、導線φjl+ φ、7.φ、3.φA4には
互いに90°ずつ位相のずれた4相駆動パルスを加える
・ただし、φ、しφ、8とφ、2.φ、4は各電極の下
のp属領域162の電位をそろえるために、それぞれ駆
動パルスのハイレベルとローレベルの電圧が違う。第7
図の破線は導線φAll φ、、がハイレベルで、導線
φ、3.φ、4がローレベルのときのp属領域162の
正孔に対する電位分布を示している。この状態で光信号
電荷の蓄積を行った後、導線φ、1.φAz+ φA3
1 φ1番に4相駆動パルスを加えると第4図中の右方
向へ光信号電荷を転送できる◎全体の動作は第6図の場
合と同じである。
That is, the conducting wire φjl+φ, 7. φ, 3. Four-phase drive pulses with phases shifted by 90 degrees from each other are applied to φA4. However, φ, φ, 8 and φ, 2. In order to equalize the potentials of the p-type region 162 under each electrode, the high-level and low-level voltages of the driving pulses are different for φ and 4, respectively. 7th
The broken lines in the figure indicate that the conductors φAll φ, , are at high level, and the conductors φ, 3. It shows the potential distribution for holes in the p-group region 162 when φ,4 is at a low level. After accumulating optical signal charges in this state, the conductors φ, 1. φAz+ φA3
1 By applying a four-phase drive pulse to No. φ1, the optical signal charge can be transferred to the right in FIG. 4. The overall operation is the same as in FIG. 6.

第7図の駆動方法の場合、前述の第4図の駆動方法に比
べ、光信号電荷の蓄積がゲート電極171〜174の下
だけでなく、ショットキ接合の電極181〜184の下
のp型領域162でも行われるので、最大電荷転送量が
大きくなり、さらに赤外光感度を持たないゲート電極1
71〜174の幅を狭くできるので開口率をさらに上げ
ることが可能になる。ただし第7図の駆動方法は第4図
の駆動方法に比して駆動パルスが複雑になる。
In the case of the driving method shown in FIG. 7, compared to the driving method shown in FIG. 162, the maximum amount of charge transfer is increased, and the gate electrode 1 does not have infrared sensitivity.
Since the widths of 71 to 174 can be narrowed, the aperture ratio can be further increased. However, the driving method shown in FIG. 7 requires more complicated driving pulses than the driving method shown in FIG.

この発明の固体撮像素子を静止物体等の観測に使用する
場合は感光部での光信号電荷蓄積時間に対し信号電荷読
出し時間を充分短くできるので蓄積部のCCD22は必
要なくなる。また、シャッタ等を使用して感光部のCC
D21の光信号電荷転送時に赤外光が入射しないような
工夫をした場合も蓄積部のCCD22は必要なくなる。
When the solid-state image sensor of the present invention is used to observe a stationary object, the signal charge readout time can be sufficiently shortened compared to the optical signal charge accumulation time in the photosensitive section, so that the CCD 22 in the storage section is not required. Also, use a shutter etc. to control the CC of the photosensitive area.
Even if measures are taken to prevent infrared light from entering during the optical signal charge transfer of D21, the CCD 22 in the storage section is no longer necessary.

なお、上記の実施例では感光部のC0D21のショット
キ接合の電極が白金硅化物PtSiで基板がSiのもの
くついて述べたが、電極の材料は他の金属硅化物もしく
は金属でもよく、基板は他の半導体でもよい。ただし、
検出可能な光の最大波長は電極の材料と基板の牛導体材
料の組合わせによりきまるので、組合わせ方によっては
検出可能な最大波長が可視領域になることもある。
In the above embodiments, the electrode of the Schottky junction of C0D21 in the photosensitive area is made of platinum silicide (PtSi) and the substrate is made of Si, but the material of the electrode may be other metal silicide or metal, and the substrate may be made of other metals. It may be a semiconductor. however,
The maximum wavelength of light that can be detected is determined by the combination of the electrode material and the conductor material of the substrate, so depending on the combination, the maximum detectable wavelength may be in the visible range.

また、赤外領域での撮像について主として説明したが、
感光部にショットキ接合を用いているので、可視領域や
可視領域以下の波長領域の撮像も可能なことは明らかで
ある。
In addition, although we mainly explained imaging in the infrared region,
Since a Schottky junction is used in the photosensitive section, it is clear that imaging in the visible region and the wavelength region below the visible region is also possible.

さらに、CCDのp型領域161〜164の相互の分離
が、n型シリコン基板15のものについて説明したが、
絶縁膜によつ′て電気的に分離してもよい。
Furthermore, although the mutual separation of the p-type regions 161 to 164 of the CCD is explained as that of the n-type silicon substrate 15,
They may be electrically isolated by an insulating film.

また、CODの埋込みチャネルがp型領域のものだけで
なく、n型領域でもよい。ただし、この場合は、p型基
板を使用し、信号電荷は電子になり、各電極に印加する
電圧は正負反転する。
Further, the buried channel of the COD is not limited to a p-type region, but may be an n-type region. However, in this case, a p-type substrate is used, the signal charges are electrons, and the voltage applied to each electrode is reversed.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、この発明は電荷の蓄積およ
び転送を行う第2の導電型の領域上に形成するショット
キ接合の電極を、CODの電極として利用し、光感度と
電荷転送を可能圧したので、開口率の大きい固体撮像素
子が得られる利点がある。
As explained in detail above, the present invention utilizes the Schottky junction electrode formed on the second conductivity type region that accumulates and transfers charge as a COD electrode, thereby increasing photosensitivity and charge transfer. Therefore, there is an advantage that a solid-state imaging device with a large aperture ratio can be obtained.

また、ショットキ接合の電極とゲート電極を交互に並べ
ることができるので、電極間の間隙を充分小さぐするこ
とが容易であり、転送効率の劣化を小さくできる効果が
ある。
Furthermore, since the Schottky junction electrodes and gate electrodes can be arranged alternately, it is easy to sufficiently reduce the gap between the electrodes, which has the effect of minimizing deterioration in transfer efficiency.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の赤外線固体撮像素子の構成図、第2図は
#I1図のA−A線における断面図、第3図はこの発明
による固体撮像素子の主要部の一実施例の構成図、第4
図は第3図のX−XfijKおける断面図、第5図Ca
) 、  (b) 、  (c)はこの発明の主要部の
製造方法の一実施例な説明する概略図、第6図はこの発
明による固体撮像素子の全体の構成の一実施例の概略図
、第7図はこの発明による固体撮像素子の主要部の他の
駆動方法を説明する概略図である。 図中、1は赤外光検出部、2は垂直シフトレジスタ、3
は水平シフトレジスタ、4はトランスファーゲート、5
は電荷検出部、6はp型シリコン基板、7は金属側電極
、8はガードリング、9はゲート電極、10はn 領域
、11はCCDのゲート電極、12はCCDのn型埋込
みチャネル、13は酸化硅素膜、14は窒化硅素膜、1
5はn型シリコン基板、20は酸化硅素膜、21は感光
部のCOD、22は蓄積部のCOD、161〜164は
p型領域、171〜174はゲート電極、181〜18
4はショットキ接合の電極、191〜194は絶縁膜、
201〜204は酸化硅素膜、211〜214は酸化硅
素膜、φ、1.φ、2.φ1..φml+φcin φ
c2は導線である。 なお、図中の同一符号は同一または相当部分を示すO 代理人 大岩増雄  (外2名) 第1図 J 第2図 第3図 入 第4図 第5図 第6図 第7図 手続補正書(自発) 昭和 6% 1月23日 事件の表示   特願昭59−129483号発明の名
称   固体撮像素子 補正をする者 事件との関係 特許出願人 住 所    東京都千代田区丸の内二丁目2番3号名
 称  (601)三菱電機株式会社代表者片山仁八部
Fig. 1 is a block diagram of a conventional infrared solid-state image sensor, Fig. 2 is a cross-sectional view taken along line A-A in Fig. #I1, and Fig. 3 is a block diagram of an embodiment of the main part of the solid-state image sensor according to the present invention. , 4th
The figure is a cross-sectional view taken along X-XfijK in Figure 3, and Figure 5 Ca.
), (b), and (c) are schematic diagrams illustrating an embodiment of the method for manufacturing the main parts of the present invention, and FIG. 6 is a schematic diagram of an embodiment of the overall configuration of the solid-state image sensor according to the present invention. FIG. 7 is a schematic diagram illustrating another method of driving the main parts of the solid-state image sensing device according to the present invention. In the figure, 1 is an infrared light detection section, 2 is a vertical shift register, and 3 is a vertical shift register.
is a horizontal shift register, 4 is a transfer gate, and 5 is a horizontal shift register.
1 is a charge detection section, 6 is a p-type silicon substrate, 7 is a metal side electrode, 8 is a guard ring, 9 is a gate electrode, 10 is an n region, 11 is a gate electrode of CCD, 12 is an n-type buried channel of CCD, 13 is a silicon oxide film, 14 is a silicon nitride film, 1
5 is an n-type silicon substrate, 20 is a silicon oxide film, 21 is a photosensitive portion COD, 22 is a storage portion COD, 161-164 are p-type regions, 171-174 are gate electrodes, 181-18
4 is a Schottky junction electrode, 191 to 194 are insulating films,
201 to 204 are silicon oxide films, 211 to 214 are silicon oxide films, φ, 1. φ, 2. φ1. .. φml+φcin φ
c2 is a conducting wire. In addition, the same reference numerals in the figures indicate the same or equivalent parts. (Spontaneous) Showa 6% Indication of January 23rd case Patent application No. 59-129483 Name of the invention Relationship to the solid-state image pickup device correction case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Jinhachibe Katayama

Claims (2)

【特許請求の範囲】[Claims] (1)第1の導電型の半導体基板と、この半導体基板の
表面領域に形成された1つまたは複数個の前記第1の導
電型と反対の導電型を有し電荷の蓄積および転送を行う
ための第2の導電型の領域と、この第2の導電型の領域
上にショットキ接合を形成するとともに光電変換を行う
ショットキ接合の電極と、前記第2の導電型の領域の少
なくとも1つに対し交互に複数個配列形成された電極列
によつて構成されるとともに前記第2の導電型の領域上
に絶縁膜を挾んで配置されたゲート電極とからなること
を特徴とする固体撮像素子。
(1) A semiconductor substrate of a first conductivity type, and one or more semiconductor substrates formed on a surface region of the semiconductor substrate having a conductivity type opposite to the first conductivity type, which accumulates and transfers charges. a Schottky junction electrode that forms a Schottky junction on the second conductivity type region and performs photoelectric conversion; and at least one of the second conductivity type regions. A solid-state imaging device comprising a plurality of electrode rows arranged alternately, and a gate electrode disposed on the second conductivity type region with an insulating film interposed therebetween.
(2)第2の導電型の領域は、絶縁膜により相互に電気
的に分離されていることを特徴とする特許請求の範囲第
(1)項記載の固体撮像素子。
(2) The solid-state imaging device according to claim (1), wherein the regions of the second conductivity type are electrically isolated from each other by an insulating film.
JP59129463A 1984-06-22 1984-06-22 Solid-state image sensor Expired - Lifetime JPH0658952B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59129463A JPH0658952B2 (en) 1984-06-22 1984-06-22 Solid-state image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59129463A JPH0658952B2 (en) 1984-06-22 1984-06-22 Solid-state image sensor

Publications (2)

Publication Number Publication Date
JPS617662A true JPS617662A (en) 1986-01-14
JPH0658952B2 JPH0658952B2 (en) 1994-08-03

Family

ID=15010114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59129463A Expired - Lifetime JPH0658952B2 (en) 1984-06-22 1984-06-22 Solid-state image sensor

Country Status (1)

Country Link
JP (1) JPH0658952B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57198656A (en) * 1981-05-15 1982-12-06 Rockwell International Corp Detecter responding to light of predetermined wavelength
JPS58206168A (en) * 1982-05-26 1983-12-01 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57198656A (en) * 1981-05-15 1982-12-06 Rockwell International Corp Detecter responding to light of predetermined wavelength
JPS58206168A (en) * 1982-05-26 1983-12-01 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof

Also Published As

Publication number Publication date
JPH0658952B2 (en) 1994-08-03

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