JPS6174197U - - Google Patents
Info
- Publication number
- JPS6174197U JPS6174197U JP15747684U JP15747684U JPS6174197U JP S6174197 U JPS6174197 U JP S6174197U JP 15747684 U JP15747684 U JP 15747684U JP 15747684 U JP15747684 U JP 15747684U JP S6174197 U JPS6174197 U JP S6174197U
- Authority
- JP
- Japan
- Prior art keywords
- abnormality
- circuits
- provided corresponding
- signal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005856 abnormality Effects 0.000 claims description 14
- 238000001514 detection method Methods 0.000 claims description 3
- 230000000452 restraining effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Alarm Systems (AREA)
Description
第１図は本考案の一実施例を示す電気的構成図
、第２図は従来例を示す第１図相当図である。
図中、１，２はセンサ、３，４はモニタランプ
（報知器）、５はブザー（補助報知器）、８は異
常検出装置、９，１０は異常判別回路、１５，１
６はインバータ（駆動回路）、１７はインバータ
（補助駆動回路）、２２，２３は信号発生回路、
２４はラツチ回路、２５，２６はＡＮＤ回路（ゲ
ート回路）を示す。
FIG. 1 is an electrical configuration diagram showing an embodiment of the present invention, and FIG. 2 is a diagram corresponding to FIG. 1 showing a conventional example. In the figure, 1 and 2 are sensors, 3 and 4 are monitor lamps (alarms), 5 is a buzzer (auxiliary alarm), 8 is an abnormality detection device, 9 and 10 are abnormality determination circuits, and 15, 1
6 is an inverter (drive circuit), 17 is an inverter (auxiliary drive circuit), 22 and 23 are signal generation circuits,
24 is a latch circuit, and 25 and 26 are AND circuits (gate circuits).
Claims (1)
センサ出力の状態に応じて異常信号を発生する複
数の異常判別回路と、これら異常判別回路に夫々
対応して設けられ前記異常信号が発生したときに
前記センサに夫々対応して設けられた複数の報知
器を駆動する複数の駆動回路と、前記複数の異常
判別回路の何れか一つから前記異常信号が発生し
たときに補助報知器を駆動する補助駆動回路とを
一つのユニツトとして構成した機器の異常検出装
置において、前記駆動回路に夫々対応して設けら
れその駆動回路の出力側に前記報知器が接続され
ていない場合に拘束信号を発生する複数の信号発
生回路と、前記拘束信号が発生したときにこれを
ラツチするラツチ回路と、前記信号発生回路に夫
々対応して設けられ前記ラツチ回路に前記拘束信
号がラツチされた状態でその信号発生回路に対応
した前記異常判別回路からの異常信号をしや断す
る複数のゲート回路とを組込んだことを特徴とす
る機器の異常検出装置。 A plurality of abnormality determination circuits are provided corresponding to the plurality of external sensors and generate abnormality signals according to the state of the sensor output, and a plurality of abnormality determination circuits are provided corresponding to each of these abnormality determination circuits and generate abnormality signals when the abnormality signals are generated. a plurality of drive circuits that drive a plurality of alarms provided corresponding to the sensors, and an auxiliary alarm that drives an auxiliary alarm when the abnormality signal is generated from any one of the plurality of abnormality determination circuits. In an abnormality detection device for equipment configured with a drive circuit as one unit, a plurality of devices are provided corresponding to the drive circuits and generate a restraint signal when the alarm is not connected to the output side of the drive circuit. a signal generating circuit, a latch circuit that latches the restraining signal when it is generated, and a signal generating circuit that is provided corresponding to each of the signal generating circuits and in a state in which the restraining signal is latched in the latch circuit. 1. An abnormality detection device for equipment, characterized in that it incorporates a plurality of gate circuits that suppress abnormality signals from the abnormality determination circuit corresponding to the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15747684U JPH0421188Y2 (en) | 1984-10-18 | 1984-10-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15747684U JPH0421188Y2 (en) | 1984-10-18 | 1984-10-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6174197U true JPS6174197U (en) | 1986-05-20 |
| JPH0421188Y2 JPH0421188Y2 (en) | 1992-05-14 |
Family
ID=30715469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15747684U Expired JPH0421188Y2 (en) | 1984-10-18 | 1984-10-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0421188Y2 (en) |
-
1984
- 1984-10-18 JP JP15747684U patent/JPH0421188Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0421188Y2 (en) | 1992-05-14 |
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