JPS6173341A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6173341A
JPS6173341A JP59194651A JP19465184A JPS6173341A JP S6173341 A JPS6173341 A JP S6173341A JP 59194651 A JP59194651 A JP 59194651A JP 19465184 A JP19465184 A JP 19465184A JP S6173341 A JPS6173341 A JP S6173341A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip
semiconductor
substrate
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59194651A
Other languages
Japanese (ja)
Inventor
Kazuo Tanaka
一雄 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59194651A priority Critical patent/JPS6173341A/en
Publication of JPS6173341A publication Critical patent/JPS6173341A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the packaging density, by connecting one terminal of a semiconductor chip to a terminal of amounting substrate with projection electrodes, and by connecting a terminal of another semiconductor chip superposed on said chip to a terminal of the mounting substrate with wires. CONSTITUTION:A mounting substrate 2 on a package substrate 1 is provided with wiring, projection electrodes, bonding pads and the like. A semiconductor chip 3 is attached to the substrate 2 by causing projection electrodes 3A to reflow with the projection electrodes on the substrate 2. A semiconductor chip 5 is bonded back to on the chip 3. Wires 6 are bonded to the chip 5 prior to the bonding between the chips 3 and 5 in order to prevent the electrodes 3a from being collapsed. By arranging the chips in this multiple-layered structure, the area of the mounting substrate can be decreased and therefore the mounting density can be increased.

Description

【発明の詳細な説明】 ［技術分野］ 本発明は、複数の半導体チップをＦｓｔＡシた半導体装
置に係り、特に、高密度実装技術に適用し、て有効な技
術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device in which a plurality of semiconductor chips are mounted using FstA, and particularly relates to a technique that is effective when applied to high-density packaging technology.

［背景技術］ 複数の半導体チップを塔載した半導体吉研（以下、マル
チチップモジュールという）は、配線。[Background technology] Semiconductor Yoshiken (hereinafter referred to as multi-chip module), which has multiple semiconductor chips mounted on it, uses wiring.

半導体素子２ポンデイングパツド等を設けた塔載用基板
となる半導体チップに、フリップ・チップ方式（以下、
ＣＣＢという）によって、桓数個の半導体チップを平面
的に電気的に接続し・でいる。A flip-chip method (hereinafter referred to as
Several semiconductor chips are electrically connected in a two-dimensional manner using CCBs (called CCBs).

そのために塔載される半導体チップの数が多くなると、
マルチチップモジュールの占める面積が増大して、塔載
用基板となる半導体チップの面積が大きくなるという問
題があった。As the number of semiconductor chips mounted increases for this purpose,
There is a problem in that the area occupied by the multi-chip module increases, and the area of the semiconductor chip serving as the mounting board increases.

なお、マルチチップモジュールの実装に関する技術は、
日経マグロウヒル社発行「日経エレクトロニクス、別冊
（マイクロデバイセズ）Ｊ１９８４年６月１１日発行、
Ｎ０９２、Ｐ２Ｓ５−ＰＩ５９に記載されている。The technology related to mounting multi-chip modules is
Published by Nikkei McGraw-Hill, "Nikkei Electronics, Separate Volume (Micro Devices) J, June 11, 1984,
N092, P2S5-PI59.

［発明の目的コ 本発明の目的は、マルチチップモジュールの実装密度を
向上することが可能な技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a technique that can improve the packaging density of multi-chip modules.

本発明の他の目的は、半導体チップの製造歩留を向上さ
せることが可能な技術を提供することにある。Another object of the present invention is to provide a technique that can improve the manufacturing yield of semiconductor chips.

本発明の前記ならびにその他の目的と新規な特徴は１本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

［発明の概要］ 本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、複数の半導体チップを塔載した１ｉｉｌ用基
板と外部機器に接続されるリードとを電気的に接続して
なるマルチチップモジュールにおいて。That is, in a multi-chip module formed by electrically connecting a 1III substrate on which a plurality of semiconductor chips are mounted and a lead connected to an external device.

前記半導体チップの一つの入出力端子と塔載用基板の入
出力端子とを突起電極で接続し、該半導体チップに第２
半導体チップを重ねて設け、該第２半導体チップの入出
力端子と塔載用基板の入出力端子とをボンデングワイヤ
で接続することにより。One input/output terminal of the semiconductor chip and the input/output terminal of the tower mounting board are connected by a protruding electrode, and a second input/output terminal is connected to the semiconductor chip.
By stacking semiconductor chips and connecting the input/output terminals of the second semiconductor chip and the input/output terminals of the mounting board with bonding wires.

半導体装置の実装密度の向上と、マルチチップモジュー
ルの小型化をはかり、かつ半導体チップの製造歩留を向
上させたものである。This aims to improve the packaging density of semiconductor devices, reduce the size of multi-chip modules, and improve the manufacturing yield of semiconductor chips.

以下、本発明の構成について１本発明を、マルチチップ
モジュールに適用し、た実施例とともに説明する。Hereinafter, the structure of the present invention will be explained along with an embodiment in which the present invention is applied to a multi-chip module.

なお、実施例の全回において、同一機能を有するものは
同一符号を付け、その繰り返し、の説明は省略する。It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and the explanation of their repetition will be omitted.

〔実施例１〕 第１図及び第２図は１本発明の実施例■のマルチチップ
モジュールを説明するための図であり、第１図は、その
マルチチップモジュールの概略構成を示す要部断面図、
第２図は、第１図に示す塔載用基板の平面図である。[Example 1] Figures 1 and 2 are diagrams for explaining a multi-chip module according to Example 2 of the present invention, and Figure 1 is a cross-sectional view of a main part showing a schematic configuration of the multi-chip module. figure,
FIG. 2 is a plan view of the mounting board shown in FIG. 1.

第１図及び第２図において、１はパッケージ基板であり
、半導体チップを塔載する塔載用基板２を埋め込むため
の凹部ＩＡが設けられている。塔載用基板２は半導体チ
ップからなっており、これには、第２図に示すように、
配線２Ａ、メモリ素子及び論理素子等を設けた領域２Ｂ
、半田等からなる突起電極２Ｃ、ボンディングパッド２
Ｄ等が設けられている。この塔載用基板２は、前記パッ
ケージ基板１の凹部ＩＡの中に接着剤で接着されている
。３は第１半導体チップであり、これに設けられている
半田等からなる突起電極３Ａと前記塔載用基板２に設け
られている突起型ｔ１２ｃとをリフローさせることによ
り、塔載用基板２に取り付けられる。４は第２半導鉢チ
ツプであり、例えばレベル変換素子等を有する半導体チ
ップである。In FIGS. 1 and 2, 1 is a package substrate, and a recess IA is provided for embedding a mounting substrate 2 on which a semiconductor chip is mounted. The mounting board 2 is made of a semiconductor chip, and as shown in FIG.
Area 2B provided with wiring 2A, memory elements, logic elements, etc.
, protruding electrode 2C made of solder etc., bonding pad 2
D etc. are provided. This mounting board 2 is bonded into the recess IA of the package board 1 with an adhesive. Reference numeral 3 designates a first semiconductor chip, and by reflowing the protruding electrode 3A made of solder or the like provided thereon and the protrusion type t12c provided on the tower mounting substrate 2, the tower mounting substrate 2 is bonded. It is attached. Reference numeral 4 denotes a second semiconductor chip, which is a semiconductor chip having, for example, a level conversion element.

４Ａは第２半導体チップ４の突起電極であり、第１半導
体チップ３と同様にして第２半導体チップ４を塔載用基
板２に取り付けるためのものである。4A is a protruding electrode of the second semiconductor chip 4, which is used to attach the second semiconductor chip 4 to the mounting substrate 2 in the same manner as the first semiconductor chip 3.

５は第３半導体チップであり、例えばＭＯＳメモリであ
る。この第３半導体チ ツブは、第１半導体チップ３の上に背中合わせに接着剤
で接着されている。第３半導体チップ５１＼の第１ワイ
ヤ６のボンディングはこの接着の前に行う。これは前記
接着後にこのワイヤボンディングを行うと、第１半導体
チップ３の突起７１！ｆＩ３Ａがつぶれてしまうからで
ある。７は第２ワイヤであり、塔載用基板２の入出力端
子とパッケージ基板１の入出力端子とを電気的に接続す
るためのものである。5 is a third semiconductor chip, for example, a MOS memory. This third semiconductor chip is bonded back to back onto the first semiconductor chip 3 with an adhesive. Bonding of the first wire 6 of the third semiconductor chip 51\ is performed before this bonding. If this wire bonding is performed after the bonding, the protrusion 71 of the first semiconductor chip 3! This is because fI3A will collapse. A second wire 7 is used to electrically connect the input/output terminals of the tower mounting board 2 and the input/output terminals of the package board 1.

このように２第３半導体チップ５を第１半導体チップ３
と背中合わせに重ねることにより、塔載用基板２の面積
を小さくする。ことができるので。In this way, the second semiconductor chip 5 is connected to the first semiconductor chip 3.
By stacking them back to back, the area of the tower mounting substrate 2 is reduced. Because you can.

半導体チップの実装密度を向上させることができる。The packaging density of semiconductor chips can be improved.

なお、前記パッケージ基体１の凹部ＩＡは、必ずしも設
ける必要はなく、平担であってもよい。Note that the recess IA of the package base 1 does not necessarily need to be provided, and may be flat.

また、前記第３半導体チップ５への第１ワイヤのボンデ
ィングを接着時に行う場合は、支持治具を第１半４体チ
ップ３と第３半導体チップ５との間に挿入して行うこと
もできる。また、前記パッケージ基板１と塔載用基板２
間に放熱用良熱伝導体を介在させて放熱を良くすること
もできる。Further, when bonding the first wire to the third semiconductor chip 5 at the time of adhesion, a support jig may be inserted between the first half-quad chip 3 and the third semiconductor chip 5. . In addition, the package substrate 1 and the tower mounting substrate 2
Heat dissipation can also be improved by interposing a good heat conductor for heat dissipation in between.

〔実施例■〕[Example ■]

第３図は、本発明の実施例■のマルチチップモジュール
の概略構成を示す要部断面図である。FIG. 3 is a sectional view of essential parts showing a schematic configuration of a multi-chip module according to Example 2 of the present invention.

本実施例■のマルチチップモジュールは、第３図に示す
ように、前記実施例Ｉのマルチチップモジュールの第２
半導体チップ４を第３半導体チップ５の上にＣＣＢによ
り接続して四重構造にしたものである。As shown in FIG. 3, the multi-chip module of this embodiment
A semiconductor chip 4 is connected to a third semiconductor chip 5 by a CCB to form a quadruple structure.

このように四重構造にすることにより、さらに塔載用基
板２の面積を低減することができる。By forming the four-layer structure in this manner, the area of the column-mounting substrate 2 can be further reduced.

また、半導体チップを小さい寸法に分割して多重構造に
することにより、半導体チップの製造時において、ウェ
ハの歩留を向上させることができる。Further, by dividing the semiconductor chip into small dimensions and forming a multilayer structure, it is possible to improve the yield of wafers during semiconductor chip manufacturing.

〔効果〕〔effect〕

以上説明したように１本願において開示された新規な技
術によれば、以下に述べるような効果を得ることができ
る。As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.

（１）マルチチップモジュールにおいて、半導体チップ
の配置を多重構造にすることにより、塔載用基板の面積
を低減することができるので、半導体チップの実装密度
を向上させることができる。(1) In a multi-chip module, by arranging the semiconductor chips in a multiplex structure, the area of the mounting board can be reduced, so the packaging density of the semiconductor chips can be improved.

（２）前記（１）により、半導体チップを小さい寸法に
分割して多重構造にすることができるので。(2) According to the above (1), the semiconductor chip can be divided into small dimensions to form a multilayer structure.

半導体チップの製造時おいて、ウェハの歩留を向上させ
ることができる。When manufacturing semiconductor chips, the yield of wafers can be improved.

（３）前記（１）により、マルチチップモジュールの小
型化がはかれる。(3) According to (1) above, the multi-chip module can be miniaturized.

以上１本発明者によってなされた発明を、前記実施例に
もとずき具体的に説明したが、本発明は、前記実施例に
限定されるものではなく、その要旨を逸脱しない範囲に
おいて、種々変形し得ることは勿論である。Although the invention made by the present inventor has been specifically explained above based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof. Of course, it can be modified.

例えば、半導体チップのレイアウトは、必要に応じて決
定し得ることはいうまでもない。For example, it goes without saying that the layout of the semiconductor chip can be determined as necessary.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図は、本発明の実施例Ｉのマルチチップ
モジュールを説明するための図であり。 第１図は、そのマルチチップモジュールの概略構成を示
す要部断面図、 第２図は、第１図に示す塔載用基板の平面図。 第３図は、本発明の実施例■のマルチチップモジュール
の概略構成を示す要部断面図である。 図中、■・・・パッケージ基板、２・・・塔載用基板、
３・・・第１半導体チップ、４・・第２半導体チップ、
５・・・第３半導体チップ、６・・・第１ワイヤ、７・
・・第２ワイヤである。 第　　　１　　図 ７円 第　　　２　　図1 and 2 are diagrams for explaining a multi-chip module of Example I of the present invention. FIG. 1 is a cross-sectional view of a main part showing a schematic configuration of the multi-chip module, and FIG. 2 is a plan view of a mounting board shown in FIG. 1. FIG. 3 is a sectional view of essential parts showing a schematic configuration of a multi-chip module according to Example 2 of the present invention. In the figure, ■...Package board, 2... Tower mounting board,
3...first semiconductor chip, 4...second semiconductor chip,
5... Third semiconductor chip, 6... First wire, 7...
...This is the second wire. Figure 1 7 yen Figure 2

Claims (1)

【特許請求の範囲】 １、複数の半導体チップを塔載した塔載用基板と外部機
器に接続されるリードとを電気的に接続してなる半導体
装置において、前記半導体チップの一つの入出力端子と
塔載用基板の入出力端子とを突起電極で接続し、該半導
体チップに第２半導体チップを重ねて設け、該第２半導
体チップの入出力端子と塔載用基板の入出力端子とをボ
ンディングワイヤで接続したことを特徴とする多重半導
体装置。 ２、前記第２半導体チップとして、入出力機能、論理機
能、記憶機能のいずれかを有する半導体チップを用いた
ことを特徴とする特許請求の範囲第１項記載の多重半導
体装置。 ３、前記塔載用基板として、配線、半導体素子、ボンデ
ィングパッド等を有する半導体チップを用いたことを特
徴とする特許請求の範囲第１項又は第２項記載の多重半
導体装置。[Claims] 1. In a semiconductor device formed by electrically connecting a mounting board on which a plurality of semiconductor chips are mounted and a lead connected to an external device, one input/output terminal of the semiconductor chip and an input/output terminal of the tower mounting board are connected by a protruding electrode, a second semiconductor chip is provided overlapping the semiconductor chip, and the input/output terminal of the second semiconductor chip and the input/output terminal of the tower mounting board are connected. A multiplex semiconductor device characterized by being connected by bonding wires. 2. The multiplex semiconductor device according to claim 1, wherein a semiconductor chip having any one of an input/output function, a logic function, and a storage function is used as the second semiconductor chip. 3. The multiplexed semiconductor device according to claim 1 or 2, wherein a semiconductor chip having wiring, semiconductor elements, bonding pads, etc. is used as the mounting substrate.
JP59194651A 1984-09-19 1984-09-19 Semiconductor device Pending JPS6173341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59194651A JPS6173341A (en) 1984-09-19 1984-09-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59194651A JPS6173341A (en) 1984-09-19 1984-09-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6173341A true JPS6173341A (en) 1986-04-15

Family

ID=16328051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59194651A Pending JPS6173341A (en) 1984-09-19 1984-09-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6173341A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420787B1 (en) 1999-06-21 2002-07-16 Shinko Electric Industries Co., Ltd. Semiconductor device and process of producing same
JP2016532309A (en) * 2013-10-15 2016-10-13 インテル・コーポレーション Magnetic shielding integrated circuit package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420787B1 (en) 1999-06-21 2002-07-16 Shinko Electric Industries Co., Ltd. Semiconductor device and process of producing same
US6548326B2 (en) 1999-06-21 2003-04-15 Shinko Electronic Industries Co., Ltd. Semiconductor device and process of producing same
JP2016532309A (en) * 2013-10-15 2016-10-13 インテル・コーポレーション Magnetic shielding integrated circuit package

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