JPS617291U

JPS617291U - Surge suppression circuit for inverter circuit

Info

Publication number: JPS617291U
Application number: JP9045284U
Authority: JP
Inventors: 広義山崎; 良矩安西
Original assignee: 三菱電機株式会社
Priority date: 1984-06-18
Filing date: 1984-06-18
Publication date: 1986-01-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のインバータ回路のサージ抑制回路を示す
接続図、第２図はこの考案によるインハータ回路のサー
ジ抑制回路の一実施例を示す接続図、第３図はこの考案
によるインバータ回路のサージ抑制回路の他の実施例を
示す接続図、第４図は第２図及び第３図におけるサージ
吸収回路ＳＡの他の例を示す接続図、第５図はこの考案
の実施例の動作を説明するための図で、各部の電圧を示
す図である。図において、１１は直流電源、１３はインダクタ、１４
は発振トランス、１８．１９はトランジスタ、２１．２
２は抵抗、２６はコンデンサ、２９はダイオード、３０
は抵抗、３１はコンデンサ、３２は放電抵抗、３３は非
直線抵抗素子、ＳＡはサージ吸収回路、３４は放電灯負
荷である。なお図中同一符号は同一又は相当部分を示す。Fig. 1 is a connection diagram showing a conventional surge suppression circuit for an inverter circuit, Fig. 2 is a connection diagram showing an embodiment of a surge suppression circuit for an in-harter circuit according to this invention, and Fig. 3 is a connection diagram showing a surge suppression circuit for an inverter circuit according to this invention. A connection diagram showing another embodiment of the suppression circuit, FIG. 4 is a connection diagram showing another example of the surge absorption circuit SA in FIGS. 2 and 3, and FIG. 5 explains the operation of the embodiment of this invention. It is a diagram showing voltages at various parts. In the figure, 11 is a DC power supply, 13 is an inductor, and 14
is an oscillation transformer, 18.19 is a transistor, 21.2
2 is a resistor, 26 is a capacitor, 29 is a diode, 30
is a resistor, 31 is a capacitor, 32 is a discharge resistor, 33 is a non-linear resistance element, SA is a surge absorption circuit, and 34 is a discharge lamp load. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims

[Claims for Utility Model Registration] (1) A surge absorption circuit connected to an inverter circuit suppresses the surge voltage repeatedly generated due to the operation of the inverter circuit, wherein the surge absorption circuit includes a diode and the diode. An inverter circuit comprising: a capacitor connected in series; a resistor connected in parallel to the capacitor through which discharge current of the capacitor flows; and a non-series resistance element connected in parallel to the capacitor. Surge suppression circuit. (2) Parallel resonance in which the inverter circuit consists of an oscillation transformer and a capacitor, with an intermediate tap connected to one terminal of the DC power supply via an inductor, and transistors at both ends connected to the other terminal of the DC power supply. The surge suppression circuit for an inverter circuit according to claim 1, which is a push-pull type transistor inverter circuit having a circuit. (3) Utility model registration claim 1, characterized in that the oscillation transformer is a leakage transformer to which a discharge lamp is connected to the secondary side, and a surge absorption circuit is connected to the secondary side of the leakage transformer. A surge suppression circuit for the inverter circuit according to item 2. (4) A surge suppression surface for an inverter circuit according to any one of claims 1 to 3, wherein the surge absorption circuit is connected to a terminal having high high frequency impedance. (5) The surge absorption circuit is connected to the primary and secondary sides of the oscillation transformer.
The surge suppression circuit for an inverter circuit according to claim 2 or 3, wherein the surge suppression circuit is connected to either of the following sides. (6) Utility model registration claims 1 to 3 characterized in that a non-linear resistance element is connected in series with a resistor.
A surge suppression circuit for an inverter circuit according to any one of paragraphs. (7) The surge suppression circuit for an inverter circuit according to claim 4, wherein the non-linear resistance element is connected in series with the resistor. (8) The surge suppression circuit for an inverter circuit according to claim 5, wherein the non-linear resistance element is connected in series with the resistor. (9) Surge in the inverter circuit according to any one of claims 1 to 3 of the utility model registration claim, characterized in that the non-linear resistance element is connected in parallel to a series circuit of a capacitor and a resistor. Inhibitory circuit. (1α Surge suppression circuit for an inverter circuit according to claim 4 of the utility model registration, characterized in that a non-linear resistance element is connected in parallel to a series circuit of a capacitor and a resistor. (11) Non-linear resistance element A surge suppression circuit for an inverter circuit according to claim 5, wherein the linear resistance element is connected in parallel to a series circuit of a capacitor and a resistor.