JPS6171660A - Improved iil lock inverter element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved IIL gate (logic inverter) and method of manufacturing the same.

As is known, 11 [gates are essentially multi-
It includes a collector transistor and another lateral transistor used as a current source, which transistors are integrated in an eight-pack density structure. Such a gate is illustrated in FIGS. 1 and 2, where the electrical graphic symbol and a cross-sectional view across the silicon chip on which it is formed are shown, respectively. In particular, in FIG. 1, a pnp lateral transistor is shown at 1 and a multi-collector npn l-transistor is shown at 2, functioning as a current source. In this diagram, the injector terminal of transistor 1 is
, the base terminal is marked 4 and the collector terminal is marked 5, while the transistor 2
The base, emitter and collector of 7, 8 and 9T- are shown respectively.

As shown, the base 4 of transistor 1 is connected to the emitter 8 of transistor 2, while the collector 5 of transistor 1 is connected to the base of transistor 2. Furthermore, the input terminals connected to the collector 5 and the base 7 are indicated at 6, while the collector 9 forms the output of the system.

FIG. 2 shows a cross-sectional view across a typical known structure. The structure includes a plurality of superimposed layers, of which the p-type substrate is subdivided by 10 and n
The buried layer of the mold is removed at 11 to simultaneously form the base 4 of transistor 1 and the emitter E3 of transistor 2 and insulate it from the top surface of the device. ? A vertical layer of n+ type (sinker) extending downward to 11 (J at 13) and a laterally insulated n-type [bitaxy] full layer is shown at 12.

Within layer 12 is a p-type region 14 which forms the base of transistor 2 and at the same time the collector 55 of transistor 1, according to the known Brainer diffusion technique;
A p-type region 15 forming the T-mitter of the transistor 1 constituting the injector is formed.Finally,
In layer 14, a D-shaped region 16 is formed forming the director of transistor 2. This structure is completed by two contacts 17, 186 and 19 for the injector, the output of the device and the input of the device, respectively. be done.

This structure is currently widely used because it requires a relatively small area and therefore provides high integration density, but is not without drawbacks. In fact, at low current levels, all collectors in the same device exhibit the same behavior, but at high current levels, the influence of the distributed resistance along the base and the base layer itself in the region essentially underlying the diffusion n+16 The influence of the relatively high resistance of

In fact, the base current flowing along the resistor reduces the voltage across the base so that the collector located farthest from the injector is not driven as does the collector located closest to the injector. Therefore, the behavior of each collector is different, and this difference in behavior becomes more noticeable as the number of collectors increases.

Therefore, the maximum number of collectors that can be installed in one device (so-called 7 fans) is limited to about 3 to 4.

The disadvantage of the pond of the element of the previous tt I'& technique is that the base contact 119, l-3 (f in 9 cho lid 1f of each collector 16 + (1 vs. If / neck is individual -) collector's switch tink Therefore, the injector 17 is far from the injector 17.
Base input contact 1 while slowest during ignition regulation
5) farthest from] Rector is the slowest during the switch-on.

Under these circumstances, the underlying problem of this invention is l11
- Retaining the characteristics of the technology while eliminating its drawbacks, e.g.
1.1 has a uniform switching action)
It is one thing to be able to provide an electrician 111-guru 1-kiryo that avoids arranging a realistic number of outgoing car J rectors according to peace of mind.

This l! l! ! A particular object of the invention consists in providing a device of the above-mentioned type which is inexpensive (1n1 manufacturing cost and easy to manufacture) with respect to known devices.

Another object of the invention consists in providing a highly reliable component with improved electrical characteristics.

The present invention also aims to provide a method for producing one or two such elements that can meet the requirements listed above.

The problems identified, the objectives outlined and others that will become apparent below are realized by an improved IIL logic inverter, which comprises a first inverting multiple-collector transistor and , a second transistor operating as a current generator;
the first and second transistors are comprised of a plurality of lying layers of two substantially opposite polarities, the plurality of lying layers forming emitter, base and collector regions of the first transistor; and forming the injector, head and collector regions of the second transistor, the rA region being connected to the input, output a3 and injector contact at the external surface of the device, and forming the injector, head and collector regions of the second transistor. The injector region is characterized in that it contains at least one buried channel extending symmetrically with respect to the rectifier region of the first transistor.

Of the song! BRIEF DESCRIPTION OF THE DRAWINGS t m Jt and its advantages will become clear from the description of a detailed but non-exclusive embodiment, shown by way of example and shown in the accompanying drawings.

C; Detailed information on Figures 1 and 2.
1. Figure ζ3 (Figures 13 and 4 will be explained here).

Referring to FIGS. 3J-3 and 4, the IIL electron current according to the present invention is of substantially p-type (nabstraight 2
0do, n''!, S'! lJi buried layer 21,
The epitaxial layer 23 and the transistor 1 are formed here.
and 2 are formed. In a particularly well-known manner, a region 24 is formed in the epitaxial layer 23 in which some phosphorus ions are implanted in order to increase the charge on the emitter of the transistor 2.

Also formed within region 24 is a p-region or layer 25 which simultaneously forms the base of transistor 2 and the collector of transistor 1. Finally, in the layer 25, an n+- region 26, which constitutes the collector of the transistor 2, is formed.

According to the essential characteristics of the invention, the injector region here includes three channels 22a, indicated by hatching in FIG. 4 and extending parallel to the epitaxial layer 23 and partially into the buried layer; 22b
, 22c. The chitenles 22a, 22b and 22c are joined together at their ends forming channels 22e and 22'' extending across them.

Especially the middle channel 2 as shown in the figure.
2b extend in a symmetrical position with respect to the collector regions arranged according to the invention in two rows parallel to each other and parallel to the central channel 22b. The two outermost channels 22a and 22C
is the collector region 2 for optimum operation of the device.
6 is of the Emi ivy layer 24, facing white, J, sea urchin - J Rector territory 1 or 26, 71 reconnaissance] ° extending in the direction -C
There is. Lateral channel 22 [(Y) Vertical channel 17 channel 22d shown in FIG.
4, and at this point an electronic device according to the light is formed. This element is the collector contact 27 (in other words, the output of the cable).

It is completed by the base connector 1-2ε3 (forming the input end T of the cable), d5 and the injector contact 31 (only shown in FIG. 4).

Therefore, as shown, injector area II
+1 by a buried structure formed from a channel extending over a fixed equal distance from the collector region 2 (3) to 1 so as to eliminate differences in the action of the individual collectors during the 8ff brightness of the device. In addition, the arrangement of the buried injector 1 and the collector area in the row of the line 1j is such that the symmetrical division of the collector 1 with respect to the base contact 1 is J -3 Base contacts 28 are centered between the rows themselves to eliminate delays in switching off the stringers. .

The buried injector structure is realized by a double insulation technique (°top-bottom insulation). In particular, the fabrication method involves pre-depositing C antimony over the entire area where the IIL gate is to be 1q. It consists of placing
During this pre-deposition of antimony, a spot injection of boron is carried out in the area where the structure of the injector layer is to be formed, which is indicated by the hunted area seen in FIG. It has a shape that

A lightly doped epitaxial layer of silicon is then grown. During successive heat treatments at high temperature J3, both the antimony and boron of the injector structure diffuse within the epitaxial layer to obtain the layers 21, 22 shown in cross-section in FIG.

Of course, due to the different diffusion properties of boron and antimony, boron will grow to about the mid-height of the epitaxial layer. After that, 71 phosphorus ions are carried out to increase the charge on the emitter of transistor 2 by increasing P1η24 by 1''.
1 apposition 1 to a3 and a vertical channel 22 for connection with the top insulation (old part 1) or jq line and injector contact where diffusion is carried out and not shown.
dlfit! Finally, a deposit of phosphorus 1 to 1 and a diffusion of boron] and diffusion are realized to form the layer 25 and the =I rectifier region 26.

All of the normal steps for completing the device are then completed.

As can be appreciated from the foregoing description, the present invention achieves its objectives. In fact, Injiektachi! ? Due to the phase Δl arrangement of the channel, collector region J3 and base contact, an IIL gate element is provided which ensures uniform V' behavior of all collectors during the switching-on and A phase of the element. In fact, it is an equal distance away from the collector area leading to pace contact 1;
On the other hand, the resistance distributed along the injector channel 22 is much lower than that of the base layer, and even the farthest collector 26 from the injector contact behaves approximately the same as the nearest collector. . In fact, the base layer was previously tested to 4-5 Ω due to the electrical properties of the layer along the buried injector channel and of the neck.
We had a resistance on the order of 7/min, while on the three channels we have a resistance of 100 ohms/min. Therefore, this allows the deposition of any desired number of collector areas (usually 10 or less) without requiring fan-out to be limited. Whereas previously when designing devices the worst performance had to be taken into account for the most advantageous collector, now the performance of different collectors is almost uniform and equal to the best behavior. , the fact of the mouth is also giving the element a better average performance.

The device according to the invention is associated with improved electrical properties compared to known devices. In fact, the illustrated deposition of an emitter layer following a top-bottom isolation approach will reduce the force coupling of the current at the base of the region lying/stuck on the channel 22b due to the neck in the emitter layer 24 on such a channel. decrease. Therefore, a higher effective gain is obtained as well as a higher switching on/'off speed compared to known devices.

The invention allows many modifications and variations without departing from the scope of the inventive concept.

Furthermore, all of the technical details are
11! C may be replaced by the details of I.

[Brief explanation of the drawing]

FIG. 1 is a wiring diagram of a +11- gate. FIG. 2 shows a series including an IIL gate according to the prior art.
FIG. FIG. 3 is a lateral sectional view of a silicon boot tube including an l1l-gate according to the present invention. FIG. 4 is a plan view of the region where the IIL gate of the present invention is formed, where the dashed line of the scale type (J, species/2
It shows the areas and their boundaries and clarifies their mutual status. In the figure, 1 is pnp lateral i~transistor,
2 is a multi-ip-collector npn transistor, 20 j
, t D type nub straight, 21 is n++ buried layer, 22
a. 22b, 22c, 22e, 22f are channels, 2
3 is an epitaxial layer, 24 is a region into which phosphorus ions are implanted, 25 is a p-type region, 26 is an n+ type region 27 is a collector contact, 28 is a space contact, and 1-131 is an injector contact. Patent Applicant: E.T., E.L., Microcho., Ltd., E.T., B.A., Agent: Patent Attorney: Kube Fukaji (
2 others)

Claims (8)

[Claims] (1) An improved IIL logic inverter device comprising a first multiple-collector inverting transistor and a second transistor operating as a current source, the first and second transistors being two substantially comprising a plurality of lying layers of opposite polarity, said plurality of lying layers forming the emitter, base and collector regions of said first transistor and forming the injector, base and injector regions of said second transistor. and forming the collector region,
the region is connected to an input, an output and an injector contact at an external surface of the element, the injector region of the second transistor having at least one region extending symmetrically with respect to the collector region of the first transistor; An improved IIL logic inverter device comprising a buried channel. 2. The logic device of claim 1, wherein the injector channel has an end that appears on an external surface of the device and is connected to the injector contact. (3) the collector regions are arranged in two substantially parallel rows spaced apart and the input contacts are of the first transistors separated by the two parallel rows of the collector regions; 2. Logic device according to claim 1, characterized in that a portion of the base region extends at least partially on an external surface of the device. (4) The injector region of the second transistor is
three buried channels extending at regular intervals from each other outside and between the rows of the collector region of the first transistor and recombining laterally from outside with respect to the row; 4. The logic device according to claim 1, wherein an end portion faces a surface of the device. (5) having a multilayer structure defining at least one major exterior surface, the structure comprising: at least one substrate of a first polarity; a buried layer of a second polarity adjacent the substrate; an epitaxial layer of substantially the second polarity with a portion adjacent to the buried layer and terminating at the external surface; and a channel structure of substantially the first polarity, the channel structure substantially buried channels that are parallel to each other and recombined together at opposite ends and extend at least partially through an epitaxial layer and said buried layer, said channel structure extending transversely to said layer and at said external surface. further comprising another layer of substantially said first polarity, having a connecting portion terminating therein, and including a portion adjacent said epitaxial layer and facing said external surface of said device; Claims 1 to 4, comprising a plurality of regions of substantially said second polarity arranged in two mutually parallel rows, thus surrounded and terminating at said external surface.
Logic element according to any of paragraphs. (6) In its cross section, the buried channels are arranged parallel to and offset from the mutually parallel rows formed by the plurality of regions.
A logic element according to any one of claims 1 to 5. (7) The logic device according to any one of claims 1 to 6, wherein the buried layer and the channel structure are formed by a top-bottom insulation technique. (8) A method for obtaining an improved IIL logic inverter device, the method comprising: pre-depositing a thin atomic layer of a first chemical element over a substrate of a first polarity;
said first chemical element is adapted to form a layer of a second polarity opposite to said first polarity, and upon said pre-deposition, parallel further comprising the step of implanting atoms of a second chemical element to form a channel, said second chemical element being adapted to substantially form said first polar layer, at high temperatures and at practical cost. growing an epitaxial layer of said second polarity resulting in the diffusion of elements of said first and second chemical elements; selectively depositing or implanting chemical elements to substantially obtain said first polarity connection channels; performing a conventional type of dielectric diffusion; and planarly diffusing other conventional layers. and completing the electronic device using a method for obtaining an improved IIL logic inverter device.