JPS6170422U - - Google Patents
Info
- Publication number
- JPS6170422U JPS6170422U JP15622884U JP15622884U JPS6170422U JP S6170422 U JPS6170422 U JP S6170422U JP 15622884 U JP15622884 U JP 15622884U JP 15622884 U JP15622884 U JP 15622884U JP S6170422 U JPS6170422 U JP S6170422U
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- dielectric layer
- delay circuit
- circuit element
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009751 slip forming Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 229910000859 α-Fe Inorganic materials 0.000 description 1
Landscapes
- Filters And Equalizers (AREA)
- Coils Or Transformers For Communication (AREA)
Description
第１図はこの考案の一実施例を示す正面図解図
である。第２図は第１図の線−における断面
図である。第３図はこの考案の背景となる定Ｋ形
フイルタを用いた遅延回路を示す回路図である。
第４図は従来の遅延回路素子の外観を示す概略斜
視図である。
図において、１０は遅延回路素子、１２はフエ
ライト、１４は第１電極、１６は誘電体層、１８
は第２電極を示す。
FIG. 1 is an illustrative front view showing one embodiment of this invention. FIG. 2 is a sectional view taken along the line - in FIG. 1. FIG. 3 is a circuit diagram showing a delay circuit using a constant K type filter, which is the background of this invention.
FIG. 4 is a schematic perspective view showing the appearance of a conventional delay circuit element. In the figure, 10 is a delay circuit element, 12 is a ferrite, 14 is a first electrode, 16 is a dielectric layer, 18
indicates the second electrode.
Claims (1)
まで連続して形成されかつインダクタンスを形成
するための第１電極、 前記磁性体の前記長手方向に間隔を隔てて、前
記第１電極上に部分的に形成される誘電体層、お
よび 前記誘電体層上に形成されかつ前記第１電極お
よび前記誘電体層と協働して静電容量を形成する
ための第２電極を備える、遅延回路素子。[Claims for Utility Model Registration] A rod-shaped magnetic body; a first electrode continuously formed on a side surface of the magnetic body from one longitudinal end to the other end for forming an inductance; a dielectric layer partially formed on the first electrode at intervals of , and a dielectric layer formed on the dielectric layer and cooperating with the first electrode and the dielectric layer to increase capacitance. A delay circuit element comprising a second electrode for forming a delay circuit element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15622884U JPH0246094Y2 (en) | 1984-10-15 | 1984-10-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15622884U JPH0246094Y2 (en) | 1984-10-15 | 1984-10-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6170422U true JPS6170422U (en) | 1986-05-14 |
| JPH0246094Y2 JPH0246094Y2 (en) | 1990-12-05 |
Family
ID=30714237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15622884U Expired JPH0246094Y2 (en) | 1984-10-15 | 1984-10-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0246094Y2 (en) |
-
1984
- 1984-10-15 JP JP15622884U patent/JPH0246094Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0246094Y2 (en) | 1990-12-05 |