JPS6169221A - Signal receiver - Google Patents

Signal receiver

Info

Publication number
JPS6169221A
JPS6169221A JP18970784A JP18970784A JPS6169221A JP S6169221 A JPS6169221 A JP S6169221A JP 18970784 A JP18970784 A JP 18970784A JP 18970784 A JP18970784 A JP 18970784A JP S6169221 A JPS6169221 A JP S6169221A
Authority
JP
Japan
Prior art keywords
current
impedance element
voltage
variable impedance
reception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18970784A
Other languages
Japanese (ja)
Other versions
JPH0455007B2 (en
Inventor
Shinichi Akano
赤野 信一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Azbil Corp
Original Assignee
Azbil Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Azbil Corp filed Critical Azbil Corp
Priority to JP18970784A priority Critical patent/JPS6169221A/en
Priority to US06/736,920 priority patent/US4623871A/en
Priority to SE8502704A priority patent/SE458972B/en
Priority to DE19853519709 priority patent/DE3519709A1/en
Priority to GB08513986A priority patent/GB2160395B/en
Publication of JPS6169221A publication Critical patent/JPS6169221A/en
Publication of JPH0455007B2 publication Critical patent/JPH0455007B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G08SIGNALLING
    • G08CTRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C19/00Electric signal transmission systems
    • G08C19/02Electric signal transmission systems in which the signal transmitted is magnitude of current or voltage

Abstract

PURPOSE:To attain a monolithic control circuit and to facilitate easy miniaturization of a signal receiver by transmitting only a current showing the signal value through an impedance element for reception to perform reception and flowing freely a power supply current to a load circuit. CONSTITUTION:A current IC flowing to a resistor RC serving as an impedance element for reception is defined as IC = (inter-line voltage VL - load side voltage VC)/RC. Therefore a current IS=IL-IC is satisfied by controlling the impedances of variable impedance element Z1 and Z2 so as to fix both the VL and VC and the controlling a current I1. In other words, a current IS flowing to a resistor RS has only a signal component of 0-16mA in case the line current IL is equal to 4-20mA, for example, by setting the current IC at a level equal to a bias component. Then the reception value can be detected by the voltage VS. Furthermore, a power supply current of maximum 4mA can be freely supplied when the current IL is equal to 4-20mA.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、工業プロセス等において、電流値により示さ
れる信号を受信し、パルプ等の制御対象機器上制御する
受信装置に関するものでめる。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a receiving device that receives a signal indicated by a current value in an industrial process or the like and controls a device to be controlled such as pulp.

〔従来の技術〕[Conventional technology]

工業プロセス等においては、パルプ等?遠隔制御する場
合、一般にポジショナと称される受傷装置が設けられ、
中央の制御装置から例えば4〜20mA(D範囲により
変化する電流値により信号音・嵌送し、これを受信装置
が受信のうえ、電流値に応じた制御上行なうものとなっ
ている。
In industrial processes etc., pulp etc.? For remote control, a wound device commonly referred to as a positioner is provided,
A signal sound is transmitted from a central control device using a current value that varies depending on a range of 4 to 20 mA (D), which is received by a receiving device and then controlled according to the current value.

しかし、従来においては、信号を示jTi、流値の伝送
用に2線式伝送路を要すると共に、受信装置側において
必要とするt源全供給するため、別途に2線式電源路を
必要としており、合計4本の線路が不可欠でろり、線路
の所要線材量および布設工数が増加し、設備費が高価と
な冬欠点ケ生じている。
However, in the past, a two-wire transmission line was required for transmitting the signals and current values, and a separate two-wire power supply line was required to supply all the necessary sources on the receiving device side. Therefore, a total of four lines are required, which increases the amount of wire required for the lines and the number of man-hours for laying them, leading to winter defects that increase equipment costs.

この対策としては、本出願人の別途出願による[受信装
置j(特願昭59−113009)Kより基本的な構成
が提案されており、これにおいては、2線式伝送路へ通
ずる4〜20 mA等として変化する電流から、0〜1
6mA等の窮屈により変化する信号値を示す電流全抽出
すると共に、4mA等のバイアス成分全抽出して局部電
源に用いるものとしている。
As a countermeasure against this, a basic configuration has been proposed in the separate application filed by the present applicant [Receiving device From the current varying as mA etc., 0 to 1
In addition to extracting all of the current, such as 6 mA, which shows a signal value that changes due to tightness, all of the bias components, such as 4 mA, are extracted and used for the local power supply.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、同出願においては、差動増幅器等音用いた第1
および第2の制御回路と、これらへ与える基準電圧全制
御する手段とを必要としており、構成が複雑化し高価に
なると共に、収容スペースの減少が困難でろり、近来益
々要求される装置の小形化全阻害する等の問題を生じて
いる。
However, in the same application, the first
This requires a second control circuit and a means for fully controlling the reference voltage applied to these circuits, making the configuration complicated and expensive, and making it difficult to reduce the housing space. This has caused problems such as total inhibition.

本発明は、従来のか\る欠点全根本的に解決する目的金
運し、前述の制御手段とはソ同等な制御f・     
  回路のみを用いるものとした極めて効果的な、受信
装置tt提供するものでわる。
The purpose of the present invention is to fundamentally solve all of the drawbacks of the conventional technology.
The present invention provides a highly effective receiving device using only circuits.

C問題点を解決するための手段〕 したがって、本発明はつぎの構成により目的を達成する
ものとしている。
Means for Solving Problem C] Therefore, the present invention achieves the object with the following configuration.

すなわち、2線式伝送路に対して第1の可変インピーダ
ンス系子および受信用のインビーダンス素子金直列に挿
入し、伝送路の線間電圧を一定化する方向へ可変インピ
ーダンス系子のインピーダンスを制御すると共に、これ
らと並列に直列のインピーダンス素子および第2の可変
インピーダンス素子による直列回路全接続し、直列のイ
ンピーダンス系子に通ずる電流金バイアス成分に応じた
一定値に保つ方向へ制御し、これらの制御を単一の制御
回路により行なうと共に、第2の可変インピーダンス素
子に対し並列に負荷回路上接続するものとしている。
In other words, the first variable impedance element and the impedance element for reception are inserted in series with the two-wire transmission line, and the impedance of the variable impedance element is adjusted in the direction of making the line voltage of the transmission line constant. At the same time, a series circuit consisting of an impedance element and a second variable impedance element connected in series is connected in parallel with these elements, and the current flowing through the series impedance element is controlled to be kept at a constant value according to the gold bias component. is controlled by a single control circuit, and is connected in parallel to the second variable impedance element on the load circuit.

〔作用〕[Effect]

したがって、受信用のインピーダンス系子には、信号値
?示す電流のみが通じ、これによって受信を行なえると
共に、負荷回路には、バイアス成分の範囲内において電
源電流を通ずることが自在となる。
Therefore, the impedance system for reception has a signal value? Only the current indicated by the signal is passed through, thereby allowing reception to be performed, and the power supply current can be freely passed through the load circuit within the range of the bias component.

〔実施例〕〔Example〕

以下、実施例を示す図によって本発明の詳細な説明する
Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

第1図は全体を示すブロック図でめり、線路端子tl 
、 ttを介して接続される2線式伝送路りは、線路L
1. Lxから々つており、これに対し第1の可変イン
ピーダンス素子(以下、素子)Z+が挿入されていると
共に、受信用のインピーダンス素子として抵抗器R3が
直列に接続されている一方、これらと並列に、直列のイ
ンピーダンス素子としての抵抗器Re  および第2の
素子22による直列回路が接続されている。
Figure 1 is a block diagram showing the whole.
, tt, the two-wire transmission line is the line L
1. A first variable impedance element (hereinafter referred to as an element) Z+ is inserted, and a resistor R3 is connected in series as a receiving impedance element, while a resistor R3 is connected in parallel with these. , a resistor Re as a series impedance element, and a series circuit including the second element 22 are connected.

また、素子z鵞と並列に制御回路CNTが負荷回路とし
て接続されており、同回路CNT Kは、線路端子tz
側側基基準して線間電圧Vt、、抵抗器Rcの負荷側電
圧Vc、抵抗器Rsの端子電圧Vs、および、後述の駆
動装&DRからの実測値が与えられ、制御回路CNTは
、電圧Vl、Vcに応じて第1および第2の制御電圧V
d+ 、 Vd2に送出し、各素子Z+、Zxのインピ
ーダンス金制御して電圧Vt、t”例えばIOV、電圧
Vat例えば■の一定値に保つと共に、電圧Vs に基
づく受信値と駆動装置DRからの実測値とに応する制御
演算、を行ない、後述の電、空室換器E/Pに対し制御
信号を送出するものとなっている。
In addition, a control circuit CNT is connected in parallel with the element z as a load circuit, and the circuit CNT K is connected to the line terminal tz.
Line voltage Vt, load side voltage Vc of resistor Rc, terminal voltage Vs of resistor Rs, and actual measured values from the drive device &DR, which will be described later, are given with respect to the side base, and the control circuit CNT calculates the voltage The first and second control voltages V according to Vl and Vc
d+, Vd2, and control the impedance of each element Z+, Zx to keep the voltages Vt, t'', for example, IOV, and the voltage Vat, for example, ■, constant values, and the received value based on the voltage Vs and the actual measurement from the drive device DR. A control calculation corresponding to the value is performed, and a control signal is sent to the electric and vacancy changer E/P, which will be described later.

こ\において、抵抗器Re に9通ずる電流Ic Ir
!。
In this case, the current Ic Ir flowing through the resistor Re
! .

次式によって示される。It is shown by the following formula.

したがって、Vt、に一定とする方向へ素子z1のイン
ピーダンスを制御すると共に、Vat一定とする方向へ
素子Z!のインピーダンスを制御し、これへ通ずる電流
Itk7XI減すれば、負荷電施工3にか\わらず電流
Icが一足となり、次式が成立−する。
Therefore, the impedance of element z1 is controlled in the direction of keeping Vt constant, and the impedance of element Z! is controlled in the direction of keeping Vat constant. If the impedance of is controlled and the current Itk7XI passing through it is reduced, the current Ic becomes one foot regardless of the load power application 3, and the following equation is established.

IL= I3 + It 4p h = Is + I
c5・、 工s= 工り一工C・・・・ (2)すなわ
ち、Ic  t−バイアス成分に等しく定めることによ
り、線路電流ILが例えば4〜20mAの場合、抵抗器
R8に通ずる電施工8 はO〜16mAの信号成分のみ
となる次め、電圧Vsにより受信値の検出を行なうこと
ができる。
IL= I3 + It 4p h = Is + I
c5., Work s = Work 1 Work C... (2) That is, by setting it equal to Ic t - bias component, when the line current IL is, for example, 4 to 20 mA, the electric work 8 connected to the resistor R8 has only a signal component of 0 to 16 mA.Next, the received value can be detected using the voltage Vs.

また、IL が4〜20mAf7)場合は、最大4mA
の電源電流を供給することが白花となる。
Also, if IL is 4 to 20mAf7), maximum 4mA
Supplying a power supply current of

なお、図上省略した中央の制御装置側では、定電流回路
により線路電流ILの送出?行なってお9、受端1QI
Iの入力インピーダンスが変化しても電流値に影’!J
’e与えることはない。
In addition, on the central control device side (not shown in the figure), the line current IL is sent out by a constant current circuit. Do 9, receiver 1QI
Even if the input impedance of I changes, it will affect the current value! J
'e never give.

また、電圧VCの変化が各負荷回路の動作に影#全与え
る場合には、電施工2の通ずる部位へ電圧安定化回路を
挿入すればよい。
Furthermore, if a change in voltage VC affects the operation of each load circuit, a voltage stabilizing circuit may be inserted into a portion where electrical construction 2 communicates.

このほか、素子Z1.Z2 としては、トランジスタ、
フォトカプラ等の制御可能な可変インピーダンス?呈す
るものを用いればよい。
In addition, element Z1. Z2 is a transistor,
Controllable variable impedance such as photo coupler? It is sufficient to use the one that presents the desired results.

第2図は、制御回路CNTのブーロック囚でめり、マイ
クロプロセッサ等のプロセッサCPUを中心とし、固定
メモIJROM、可変メモIJRAM、アナ−1ログ・
ディジタル変換器(以下、ADC)A/D。
Figure 2 shows the block diagram of the control circuit CNT, processor CPU such as microprocessor, fixed memory IJROM, variable memory IJRAM, analog 1 log, etc.
Digital converter (hereinafter referred to as ADC) A/D.

ディジタル・アナログ変換器(以下、DAC)D/A1
〜D/As k周辺に配したうえ、これらを母線により
接続しており、固定メモIJROM中の命令全プロセッ
サCPUが実行し、所定のデータ全可変メモIJRAM
ヘアクセスしながら制御動作上行なうものとなっている
Digital to analog converter (hereinafter referred to as DAC) D/A1
~D/Ask are arranged around the k and are connected by a bus line, so that all the instructions in the fixed memory IJROM are executed by the processor CPU, and the predetermined data are transferred to the fully variable memory IJRAM.
Control operations are performed while accessing the

また、第1図に示す電圧VCは、電圧安定化部REGに
おいて安定化されたうえ、局部電源Eとして各部へ供給
されるものとなっている。
Further, the voltage VC shown in FIG. 1 is stabilized in the voltage stabilizing section REG, and is then supplied as a local power source E to each section.

一方、AD C−A/Dの入力側にに、プロセッサCP
Uにより制御されるマルチプレクサMPXが設けてあり
、これによって各電圧VL、Vc、Vsおよび駆動装置
DRからの実測値が順次にかつ反復して選択され、AD
C・A/Dによジデイジタル信号へ各個に変換されてか
ら、プロセッサCPUへ与えられるものとなっており、
これらに応じてプロセッサCPUがDAC・D/A l
〜D/Asへ制御データを与えるため、アナログ信号へ
変換され念制御電圧Vt+ 、Vdz および電空変換
器E/Pに対する制御信号が送出される。
On the other hand, there is a processor CP on the input side of the ADC-A/D.
A multiplexer MPX controlled by U is provided, by means of which each voltage VL, Vc, Vs and the actual value from the drive DR is sequentially and iteratively selected and
After each signal is converted into a digital signal by the C/A/D, it is sent to the processor CPU.
Depending on these, the processor CPU
In order to provide control data to ~D/As, it is converted into an analog signal and a control signal for the control voltages Vt+, Vdz and the electro-pneumatic converter E/P is sent out.

第3因は、プロセッサCPUによる制御状況のフローチ
ャートでめり、マルチプレクサMPXおよびADC−A
/D を介−j6電圧SVL取込#101七行なってか
ら、めらかしめ固定メモIJROM中へ格納してるる第
1の基準電圧Vr+  との比較にJ−り ’VL =
 Vrl?“102 を判断し、CレカN(NO)でろ
ればVLの値に応じて制御電圧%Vd。
The third reason is that the flowchart of the control situation by the processor CPU is incorrect, and the multiplexer MPX and ADC-A
After the seventh line of #101, the voltage SVL is fetched via /D, and compared with the first reference voltage Vr+ stored in the smooth fixed memory IJROM.
Vrl? "102" is judged, and if it is negative (NO), the control voltage %Vd is determined according to the value of VL.

修正”103を行ない、ステップ102 がY(YES
)  となるまでこれを反復する。
Modify "103" and step 102 is YES.
) Repeat this until .

ついで、ステップ101  と同様に電圧1vC取込”
 111 k行なったうえ、ステップ102と同 様に
第2の基準電圧Vr2 との比較により’Vc= Vr
+ 7112 k判断し、CれがNのときはステップ1
03 と同じく、これがYとなるまで制御電圧’Vd2
修正”113’に行なう。
Next, in the same way as step 101, take in a voltage of 1vC.
111 k, and as in step 102, by comparing with the second reference voltage Vr2, 'Vc=Vr
+ 7112 k Judgment, if C is N, step 1
03, control voltage 'Vd2 until this becomes Y
Make the correction "113".

以上によ!1lVyVct一定としてから、ステップ1
01 と同様に電圧’ Vs取込” 121.および、
駆動装置DRからのS実測値取込“122を行ない、こ
れらに応じて1制御演算”123i行なったうえ、DA
C−D/As’を介する を制御信号送出″124 ’
i行ない、ステップ101以降を反復する。
That’s all! After setting 1lVyVct constant, step 1
Similarly to 01, voltage 'Vs capture' 121. and,
After taking in the S actual measurement value from the drive device DR ``122'' and performing 1 control calculation 123i according to these, the DA
Control signal is sent via CD/As'``124''
i, and repeat steps 101 and subsequent steps.

第4図は、受信装置側の全構#:?示すブロック図で6
9、第1図に示す受信装置REからの受信出力は電空変
換器E/Pへ与えられ、こCにおいて、圧気Pが受信出
力に応じた圧力となり、エアシリンダ等の駆動装fDR
へ送出され、これがパルプ■を駆動して開度全制御する
と共に、駆動軸と連結されたポテンショメータ等によジ
、現在の開度が実測値として検出され、受信装置REへ
与えられるものとなっている。
Figure 4 shows the entire structure of the receiving device #:? 6 in the block diagram shown
9. The received output from the receiving device RE shown in FIG.
This drives the pulp ■ to fully control the opening, and the current opening is detected as an actual value by a potentiometer connected to the drive shaft, and is given to the receiving device RE. ing.

第5図および第6図は、他の冥施例を示す第1図と同様
なブロック図でろり、第5図においては、抵抗器Rck
線路端子t!側へ挿入し、第6図では、更に抵抗器Rs
i線路線路端子側1側入しているほかは第1図と同様で
ある。
5 and 6 are block diagrams similar to FIG. 1 showing other embodiments; in FIG. 5, the resistor Rck
Railway terminal t! In FIG. 6, the resistor Rs
It is the same as in Fig. 1 except that the i-line terminal side 1 is inserted.

なお、制御回路CNTは、抵抗器Rs、Rcの挿入位置
に応じて各電圧の検出基準電位を選定する必要がめり、
これにしたがって、第2図の構成?若干変更すればよい
Note that the control circuit CNT is required to select the detection reference potential of each voltage depending on the insertion position of the resistors Rs and Rc.
According to this, the configuration of Figure 2? Just make some changes.

したがって、単一の制御回路CNTのみにより目的が達
せられると共に、同回路CNT Hすべてがディジタル
回路により槽底されるため、制御状況が安定となり、か
つ、小形化が容易となる。
Therefore, the purpose is achieved with only a single control circuit CNT, and all of the circuits CNT H are controlled by digital circuits, so that the control situation becomes stable and miniaturization becomes easy.

たyし、抵抗器Rsの代りにダイオード等のインピーダ
ンス素子、るるいは、厘W、冗流値を検出する回路を用
いてもよく、抵抗器Rc としては、定電圧ダイオード
環上用いることもできる。
However, instead of the resistor Rs, an impedance element such as a diode, or a circuit for detecting the redundant current value may be used, and a constant voltage diode may be used as the resistor Rc. can.

なお、線路を流鉱、負荷回路の所要電源を流に応じてバ
イアス成分紫定めればよく、モータ等全負荷回路とじて
使用することもできる。
In addition, it is only necessary to set the bias component purple according to the flow of the line and the required power source of the load circuit according to the flow, and it is also possible to use it as a full load circuit such as a motor.

また、第4図においては、モータ等により駆動全行なう
ものとしてもよく、パルプVのほか、ダンパ、ポンプ等
?制御対象機器としても同様でるり、本発明は種々の変
形が自在でるる。
In addition, in FIG. 4, the entire drive may be performed by a motor or the like, and in addition to the pulp V, a damper, a pump, etc.? Similarly, the present invention can be modified in various ways as well as the equipment to be controlled.

〔発明の効果〕〔Effect of the invention〕

以上の説明により明らかなとお9本発明によれば、制御
回路が単一となり、小形化か容易となる次め、各種の制
御対象機器に対する制御および電t       源供
給上顕著な効果が得られる。       。
As is clear from the above description, according to the present invention, the control circuit is single, it can be easily miniaturized, and significant effects can be obtained in terms of control and power supply to various devices to be controlled. .

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の実施例を示し、第1図は全体のブロック図
、第2図は制御回路のブロック図、第3図は制御状況の
フローチャート、第4図は受信装置側の全構成金量すブ
ロック図、第5図および第6図は他の実施例?示す第1
図と同様なブロック図でbる。 L・・・・2線式伝送路、ZI+Z2  ・・・・素子
(可変インピーダンス素子)、Rs 、 Re  ・・
・・抵抗器(インピーダンスi子)、CNT  ・・・
・制御回路(負荷回路)、CPU・・・・ プロセッサ
、ROM  ・・・・固定メモリ、RAM  ・・・・
可変メモIJ、MPX  −・・・マルチプレクサ、A
/D ・・−・ADC(アナログ・ディジタル変換器)
、D/A菖〜D /A3  ・・・・DAC(ディジタ
ル・アナログ変換器)、VL・・・・線間電圧、Ic 
・・・・電流。
The figures show an embodiment of the present invention, in which Fig. 1 is an overall block diagram, Fig. 2 is a block diagram of the control circuit, Fig. 3 is a flowchart of the control situation, and Fig. 4 is the total amount of components on the receiving device side. Are the block diagrams shown in Figures 5 and 6 for other embodiments? 1st to show
A block diagram similar to that shown in FIG. L...2-wire transmission line, ZI+Z2...element (variable impedance element), Rs, Re...
・Resistor (impedance I-piece), CNT ・・
・Control circuit (load circuit), CPU... Processor, ROM...Fixed memory, RAM...
Variable memory IJ, MPX - multiplexer, A
/D...ADC (Analog-to-digital converter)
, D/A iris~D/A3...DAC (digital-to-analog converter), VL...line voltage, Ic
...Current.

Claims (1)

【特許請求の範囲】[Claims] 2線式伝送路へ通ずる線路電流の電流値により示される
信号を受信する装置において、前記伝送路に対し直列に
挿入された第1の可変インピーダンス素子と、該可変イ
ンピーダンス素子と直列に接続された受信用のインピー
ダンス素子と、前記第1の可変インピーダンス素子およ
びインピーダンス素子に対し並列に接続された直列のイ
ンピーダンス素子および第2の可変インピーダンス素子
による直列回路と、前記伝送路の線間電圧を一定化する
方向へ前記第1の可変インピーダンス素子のインピーダ
ンスを制御すると共に前記直列のインピーダンス素子に
通ずる電流値を一定化する方向へ前記第2の可変インピ
ーダンス素子のインピーダンスを制御する制御回路と、
前記第2の可変インピーダンス素子と並列に接続された
負荷回路とを備えたことを特徴とする受信装置。
A device for receiving a signal indicated by a current value of a line current passing through a two-wire transmission line, comprising: a first variable impedance element inserted in series with the transmission line; and a first variable impedance element connected in series with the variable impedance element. a series circuit including a receiving impedance element, a series impedance element and a second variable impedance element connected in parallel to the first variable impedance element and the impedance element, and constant line voltage of the transmission line; a control circuit that controls the impedance of the first variable impedance element in a direction to make the impedance of the first variable impedance element constant, and controls the impedance of the second variable impedance element in a direction that makes the current value flowing through the series impedance element constant;
A receiving device comprising a load circuit connected in parallel with the second variable impedance element.
JP18970784A 1984-06-04 1984-09-12 Signal receiver Granted JPS6169221A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP18970784A JPS6169221A (en) 1984-09-12 1984-09-12 Signal receiver
US06/736,920 US4623871A (en) 1984-06-04 1985-05-22 Receiving apparatus
SE8502704A SE458972B (en) 1984-06-04 1985-05-31 DIALOGUE PROCEDURE AND DEVICE FOR IMPLEMENTATION OF THE PROCEDURE
DE19853519709 DE3519709A1 (en) 1984-06-04 1985-06-01 Dialog method and device for carrying out this method
GB08513986A GB2160395B (en) 1984-06-04 1985-06-04 Receiving apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18970784A JPS6169221A (en) 1984-09-12 1984-09-12 Signal receiver

Publications (2)

Publication Number Publication Date
JPS6169221A true JPS6169221A (en) 1986-04-09
JPH0455007B2 JPH0455007B2 (en) 1992-09-02

Family

ID=16245846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18970784A Granted JPS6169221A (en) 1984-06-04 1984-09-12 Signal receiver

Country Status (1)

Country Link
JP (1) JPS6169221A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002075472A3 (en) * 2001-03-20 2003-05-08 Pepperl & Fuchs Method and device for inputting data into an electronic data processing device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56145495A (en) * 1980-04-11 1981-11-12 Yokogawa Electric Works Ltd 2-wire type transmitter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56145495A (en) * 1980-04-11 1981-11-12 Yokogawa Electric Works Ltd 2-wire type transmitter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002075472A3 (en) * 2001-03-20 2003-05-08 Pepperl & Fuchs Method and device for inputting data into an electronic data processing device
US6853931B2 (en) 2001-03-20 2005-02-08 Pepperl + Fuchs Gmbh Method and device for inputting data into an electronic data processing device

Also Published As

Publication number Publication date
JPH0455007B2 (en) 1992-09-02

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