JPS6168619A - Automatic powering-on mechanism - Google Patents
Automatic powering-on mechanismInfo
- Publication number
- JPS6168619A JPS6168619A JP60193729A JP19372985A JPS6168619A JP S6168619 A JPS6168619 A JP S6168619A JP 60193729 A JP60193729 A JP 60193729A JP 19372985 A JP19372985 A JP 19372985A JP S6168619 A JPS6168619 A JP S6168619A
- Authority
- JP
- Japan
- Prior art keywords
- power
- time
- external storage
- storage device
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Power Sources (AREA)
- Direct Current Feeding And Distribution (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は計算機システム等に接続し、システムの電源を
目動的に投入する自動電源投入機構に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an automatic power-on mechanism that is connected to a computer system or the like and intentionally turns on the power of the system.
図１は従来の自動電源投入機構の一実施例の接続を示す
。FIG. 1 shows the connections of one embodiment of a conventional automatic power-on mechanism.
自動電源投入機構１は、電源投入日時を記憶する電源投
入スケジー−ル記憶部２と、時間を計時する時計部６と
、比較回路４と、リレー駆動回路５と、それらに給電す
る電源６で構成され、電源投入スケジー−ル記憶部２か
らの電源投入時刻Ｈと、時計部３からのその時の時刻Ｎ
Ｔとを比較回路４で比較し、一致がとれた時Ｋ 一致信
号ＣＭＰを発生させ、ＣＭＰ信号でリレー駆動回路５を
動作させ、リレー接点信号ＰＯＮで処理装置の電源８を
投入する自動電源投入機構がある。この場合、電源投入
スケジー−ル記憶ｓ２かもの電源投入時刻と、時計部か
らのその時の時間とを比較回路４で処理装置の電源がオ
フの時にも比較していなければならないため、一般的に
計算機等の処理装置が有している処理開始日時や経過時
間を表示するための時計機構、演算機構を使用すること
ができない欠点がありた。The automatic power-on mechanism 1 includes a power-on schedule storage section 2 that stores the power-on date and time, a clock section 6 that measures time, a comparator circuit 4, a relay drive circuit 5, and a power source 6 that supplies power to them. The power-on schedule is configured such that the power-on time H from the power-on schedule storage section 2 and the current time N from the clock section 3 are
Comparison circuit 4 compares K with T, and when a match is found, K generates a match signal CMP, operates the relay drive circuit 5 with the CMP signal, and turns on the power 8 of the processing device with the relay contact signal PON. Automatic power-on. There is a mechanism. In this case, the comparison circuit 4 must compare the power-on time in the power-on schedule memory s2 with the current time from the clock unit even when the power to the processing device is off, so generally speaking There is a drawback that a clock mechanism or arithmetic mechanism for displaying the processing start date and time and elapsed time that a processing device such as a computer has cannot be used.
（発明の目的〕
本発明の目的は処理装置が有する時計機構、演算機構お
よび、処理装置に接続されている外部記憶装置を使用す
ることにより、自動電源投入機構に固有な構成品を減ら
すことにある。(Object of the Invention) The object of the present invention is to reduce the number of components unique to the automatic power-on mechanism by using the clock mechanism, calculation mechanism, and external storage device connected to the processing device. be.
本発明は処理装置の演算結果をセットできるカウンター
回路を設け、処理装置の電源がオンの時Ｋ、処理装置の
時計機構からの時刻と、外部記憶装置に記憶しである電
源投入時刻とを処理装置の演算機構を使用して、電源投
入時間を演算し、その結果をカウンター回路にセットし
。The present invention provides a counter circuit that can set the calculation results of the processing device, and when the power of the processing device is turned on, processes the time from the clock mechanism of the processing device and the power-on time stored in an external storage device. Use the device's calculation mechanism to calculate the power-on time and set the result to the counter circuit.
カウンター回路で電源投入時間を計時することにより、
目動電源投入機構に固有な時計機構、電源投入スケジュ
ール記憶部を不用にした。By measuring the power-on time with a counter circuit,
The clock mechanism and power-on schedule storage unit unique to the automatic power-on mechanism are no longer required.
〔発明の実施例〕 以下、本発明の一実施例を第２図により説明する。[Embodiments of the invention] An embodiment of the present invention will be described below with reference to FIG.
第２図において、自動電源投入機構１０は一定間隔のパ
ルス信号を発生させるパルス発生回路１１と、１１かも
のパルス信号Ｐによりカウントするカウンター回路１２
と、リレー駆動口Ｎ １５と、上記ＩＱ、１１，１２．
１３に給電する電ｆｐ、１４により構成される。In FIG. 2, the automatic power-on mechanism 10 includes a pulse generation circuit 11 that generates pulse signals at regular intervals, and a counter circuit 12 that counts based on 11 pulse signals P.
, relay drive port N 15, and the above IQ, 11, 12 .
It is configured by a power supply fp, which supplies power to 13, and 14.
処理装置１５は時間を計時する時計部１６と、演算部１
７と、処理装置の電源１８で構成される。処理装置１５
に外部記憶装置１９が接続される。外部記憶装置１９に
電源投入スケジュールを記憶してお（。The processing device 15 includes a clock section 16 that measures time and a calculation section 1.
7 and a power supply 18 for the processing device. Processing device 15
An external storage device 19 is connected to. The power-on schedule is stored in the external storage device 19 (.
処理装置の電源１８をオフするに先だち、電源投入スケ
ジュールを記憶している外部記憶装置１９から電源投入
時刻ＰＴと、処理装置の時計機構１６のその時の時刻Ｎ
Ｔとを演算部１７により、何時間後に電源を投入するか
を演算し、その結果ｍとする発振回路１１の）くルス間
隔をｔとすると、ｍｔ−Ｎとなるカウント数Ｎをカウン
ター回路１２にセットする。Prior to turning off the power 18 of the processing device, the power-on time PT and the current time N of the clock mechanism 16 of the processing device are retrieved from the external storage device 19 that stores the power-on schedule.
The calculation unit 17 calculates how many hours later the power should be turned on, and the result is m.If the pulse interval of the oscillation circuit 11 is t, then the counter circuit 12 calculates the count number N, which is mt-N. Set to .
カウンター回路１２はパルス信号Ｐにより−１するよう
にしておく。The counter circuit 12 is set to -1 by the pulse signal P.
カウンター回路１２にＮがセットされた後に、処理装置
１５の電源１８はオフされる。After N is set in the counter circuit 12, the power supply 18 of the processing device 15 is turned off.
自動電源投入機構１０は電源１８とは別の電源１１によ
り動作しているため、電源１８がオフされても、動作し
続ける。Since the automatic power-on mechanism 10 is operated by a power source 11 different from the power source 18, it continues to operate even if the power source 18 is turned off.
カウンターの内容が正数Ｏから負数になる時にボロー信
号Ｂが発生する。A borrow signal B is generated when the contents of the counter change from a positive number O to a negative number.
信号Ｂが発生した時に電源投入時刻になるようにＮを設
定しであるので、信号ＢＫより、リレー駆動回路１３を
動作させ、電源投入信号ＰＯＮを処理装置の電源１８に
送り、電源１８を′オンする。Since N is set so that the power-on time is reached when the signal B is generated, the relay drive circuit 13 is operated from the signal BK, and the power-on signal PON is sent to the power supply 18 of the processing device, and the power supply 18 is turned on. Turn on.
カウンター回路１２を設けたことにより、電源１８がオ
ンの時に電源投入時間を演算し、カウンター回路にセッ
トしてしまい、その後はカウンター回路側で・計時する
ため、電源投入スケジュールは外部記憶装置１９を、そ
の時の時刻は処理装置の時計機構を使用でき、電源投入
時間は処理装置の演算機構を使用し演算できるようにな
る。By providing the counter circuit 12, when the power supply 18 is on, the power-on time is calculated and set in the counter circuit. After that, the counter circuit side measures the time, so the power-on schedule is stored in the external storage device 19. The time at that time can be calculated using the clock mechanism of the processing device, and the power-on time can be calculated using the calculation mechanism of the processing device.
〔発明の効果〕・
本発明によれば、電源投入スケジュールの記憶は外部記
憶装置を、その時の時刻は処理装置の時計機構を使用で
きることになるので、自動電源投入機構に固有な、電源
投入スケジュール記憶部、時計部が不用となる。[Effects of the Invention]- According to the present invention, the power-on schedule can be stored in an external storage device, and the time at that time can be stored in the clock mechanism of the processing device. The memory section and clock section are no longer needed.
第１図は従来の自動電源投入機構の一実施例を示す１０
７２図、第２図は本発明の一実施例を示す１０７２図で
ある。
１．１０・・・・・・自動電源投入機構２・・・・・・
電源投入スケジュール記憶部３．１６・・・・・・時計
機構
４・・・・・・比較回路
５．１３・・・・・・リレー駆動回路
（Ｓ、８．ｉｌ、１８・・・・・・電源７．１５・・・
・・・処理装置
１１・・・・・発振回路
１２・・・・・・カウンター回路
１９・・・・・・外部記憶装置FIG. 1 shows an example of a conventional automatic power-on mechanism.
FIG. 72 and FIG. 2 are diagrams 1072 showing one embodiment of the present invention. 1.10... Automatic power-on mechanism 2...
Power-on schedule storage unit 3.16... Clock mechanism 4... Comparison circuit 5.13... Relay drive circuit (S, 8.il, 18...・Power supply 7.15...
... Processing device 11 ... Oscillation circuit 12 ... Counter circuit 19 ... External storage device
Claims (1)
処理装置に接続される外部記憶で構成される計算機シス
テム等に接続し、外部記憶装置に一定期間の電源投入ス
ケジュールを記憶し、処理装置の時計機構からの時刻と
、外部記憶装置からの電源投入スケジュールを処理装置
の演算機構を使用して電源投入時間を演算し、その結果
をセットできるカウンター回路を設け、一定間隔のパル
ス信号でカウントし、カウンターが一定数になつたとき
にシステムの電源を投入することを特徴とする自動電源
投入機構。1. Connect to a computer system, etc., consisting of a processing device with a clock mechanism and arithmetic mechanism, and an external storage connected to the processing device, store a power-on schedule for a certain period in the external storage device, and Using the time from the clock mechanism and the power-on schedule from the external storage device, the power-on time is calculated using the processing unit's arithmetic mechanism, and a counter circuit is provided that can set the results, and counts using pulse signals at regular intervals. , an automatic power-on mechanism characterized by powering on the system when the counter reaches a certain number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60193729A JPS6168619A (en) | 1985-09-04 | 1985-09-04 | Automatic powering-on mechanism |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60193729A JPS6168619A (en) | 1985-09-04 | 1985-09-04 | Automatic powering-on mechanism |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6168619A true JPS6168619A (en) | 1986-04-09 |
Family
ID=16312833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60193729A Pending JPS6168619A (en) | 1985-09-04 | 1985-09-04 | Automatic powering-on mechanism |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6168619A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6329822A (en) * | 1986-07-24 | 1988-02-08 | Toshiba Corp | Automatic power supply control system |
| JPH0397726U (en) * | 1990-01-18 | 1991-10-08 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54137942A (en) * | 1978-04-19 | 1979-10-26 | Toshiba Corp | Home computer with timer |
| JPS5588111A (en) * | 1978-12-27 | 1980-07-03 | Fujitsu Ltd | Control system for power feed time |
-
1985
- 1985-09-04 JP JP60193729A patent/JPS6168619A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54137942A (en) * | 1978-04-19 | 1979-10-26 | Toshiba Corp | Home computer with timer |
| JPS5588111A (en) * | 1978-12-27 | 1980-07-03 | Fujitsu Ltd | Control system for power feed time |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6329822A (en) * | 1986-07-24 | 1988-02-08 | Toshiba Corp | Automatic power supply control system |
| JPH0397726U (en) * | 1990-01-18 | 1991-10-08 |
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