JPH0397726U - - Google Patents

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Publication number
JPH0397726U
JPH0397726U JP367790U JP367790U JPH0397726U JP H0397726 U JPH0397726 U JP H0397726U JP 367790 U JP367790 U JP 367790U JP 367790 U JP367790 U JP 367790U JP H0397726 U JPH0397726 U JP H0397726U
Authority
JP
Japan
Prior art keywords
circuit
power supply
time data
built
switching circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP367790U
Other languages
Japanese (ja)
Other versions
JP2548626Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990003677U priority Critical patent/JP2548626Y2/en
Publication of JPH0397726U publication Critical patent/JPH0397726U/ja
Application granted granted Critical
Publication of JP2548626Y2 publication Critical patent/JP2548626Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例によるコンピユータ
内蔵機器の電源制御装置の構成を示す機能ブロツ
ク図、第２図及び第３図は各々上記装置のスケジ
ユール作成及びアラーム設定の動作フローを示す
図である。 １……パソコン（コンピユータ内蔵機器）、２
……機器用電源回路、３……スイツチング回路、
４……タイマー回路、５……時刻データ発生手段
、６……ラツチ回路、７……電源回路、８……切
断信号発生手段。 FIG. 1 is a functional block diagram showing the configuration of a power supply control device for a computer built-in device according to an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing the operational flow of schedule creation and alarm setting of the device, respectively. be. 1... Personal computer (equipment with built-in computer), 2
...Equipment power supply circuit, 3...Switching circuit,
4... Timer circuit, 5... Time data generating means, 6... Latch circuit, 7... Power supply circuit, 8... Cutting signal generating means.

Claims (1)

【実用新案登録請求の範囲】 (1) 内蔵コンピユータによつて所定の処理を行
う機器１に通電する機器用電源回路２と、 該機器用電源回路２を接続・切断するスイツチ
ング回路３と、 上記機器１内蔵コンピユータに設けられ、該機
器１の動作中に上記スイツチング回路３の次回接
続動作時刻データを発生する時刻データ発生手段
５と、 該時刻データ発生手段５からの時刻データを入
力とし、時刻を計数するとともに上記時刻データ
に対応した時刻に上記スイツチング回路３を接続
動作させるタイマー回路４と、 上記スイツチング回路３及びタイマー回路４に
常時通電する電源回路７とを備えたことを特徴と
するコンピユータ内蔵機器の電源制御装置。 (2) 上記時刻データ発生手段５はさらに上記機
器１の動作中に上記スイツチング回路４の切断動
作時刻データを発生する機能を有し、 上記タイマー回路４はさらに上記時刻データ発
生手段５から入力される切断動作時刻データに応
じて上記スイツチング回路３を切断動作させる機
能を有することを特徴とする請求項(1)記載のコ
ンピユータ内蔵機器の電源制御装置。 (3) 上記機器１内蔵コンピユータ内に設けられ
、該機器１の動作中に上記機器用電源回路２の切
断信号を発生する切断信号発生手段８と、 該切断信号をラツチし、上記スイツチング回路
３を直接切断動作させるラツチ回路６とを備え、 上記電源回路７が上記ラツチ回路６に常時通電
することを特徴とする請求項(1)又は(2)記載のコ
ンピユータ内蔵機器の電源制御装置。[Scope of Claim for Utility Model Registration] (1) A device power supply circuit 2 that energizes a device 1 that performs predetermined processing using a built-in computer, a switching circuit 3 that connects and disconnects the device power supply circuit 2, and the above. a time data generating means 5 provided in the computer built in the device 1 and generating time data for the next connection operation of the switching circuit 3 while the device 1 is in operation; A computer comprising: a timer circuit 4 that counts the switching circuit 3 and connects and operates the switching circuit 3 at a time corresponding to the time data; and a power supply circuit 7 that constantly energizes the switching circuit 3 and the timer circuit 4. Power control device for built-in equipment. (2) The time data generating means 5 further has a function of generating disconnection operation time data for the switching circuit 4 while the device 1 is in operation, and the timer circuit 4 further receives input from the time data generating means 5. 2. The power supply control device for a computer built-in device according to claim 1, further comprising a function of causing the switching circuit 3 to perform a disconnection operation in accordance with disconnection operation time data. (3) disconnection signal generating means 8 provided in the computer built in the device 1 and generating a disconnection signal for the device power supply circuit 2 while the device 1 is in operation; A power supply control device for a device with a built-in computer according to claim 1 or 2, further comprising: a latch circuit (6) that directly disconnects the power source, and wherein the power supply circuit (7) always energizes the latch circuit (6).
JP1990003677U 1990-01-18 1990-01-18 Power control device for computer built-in equipment Expired - Fee Related JP2548626Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990003677U JP2548626Y2 (en) 1990-01-18 1990-01-18 Power control device for computer built-in equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990003677U JP2548626Y2 (en) 1990-01-18 1990-01-18 Power control device for computer built-in equipment

Publications (2)

Publication Number Publication Date
JPH0397726U true JPH0397726U (en) 1991-10-08
JP2548626Y2 JP2548626Y2 (en) 1997-09-24

Family

ID=31507484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990003677U Expired - Fee Related JP2548626Y2 (en) 1990-01-18 1990-01-18 Power control device for computer built-in equipment

Country Status (1)

Country Link
JP (1) JP2548626Y2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58168118A (en) * 1982-03-30 1983-10-04 Fujitsu Ltd Automatic power supply disconnecting and controlling system
JPS6168619A (en) * 1985-09-04 1986-04-09 Hitachi Ltd Automatic powering-on mechanism
JPS6170227U (en) * 1984-10-16 1986-05-14

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58168118A (en) * 1982-03-30 1983-10-04 Fujitsu Ltd Automatic power supply disconnecting and controlling system
JPS6170227U (en) * 1984-10-16 1986-05-14
JPS6168619A (en) * 1985-09-04 1986-04-09 Hitachi Ltd Automatic powering-on mechanism

Also Published As

Publication number Publication date
JP2548626Y2 (en) 1997-09-24

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