JPS6167929A - Plastic sealed ic - Google Patents

Plastic sealed ic

Info

Publication number
JPS6167929A
JPS6167929A JP59191293A JP19129384A JPS6167929A JP S6167929 A JPS6167929 A JP S6167929A JP 59191293 A JP59191293 A JP 59191293A JP 19129384 A JP19129384 A JP 19129384A JP S6167929 A JPS6167929 A JP S6167929A
Authority
JP
Japan
Prior art keywords
lead
lead frame
leads
wire
plastic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59191293A
Other languages
Japanese (ja)
Inventor
Seisaku Yamanaka
山中　正策
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP59191293A priority Critical patent/JPS6167929A/en
Publication of JPS6167929A publication Critical patent/JPS6167929A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To lengthen the service life of the lead frame of a plastic sealed IC in vapor and to enable to improve the reliability of the IC by a method wherein a stepping is provided at the intermediate parts of the inner leads of the leads frame and the wire-bonding area of the point part of each inner lead is made higher than the other part of the lead frame on the side of the semiconductor placing part. CONSTITUTION:The steppings 9 of the inner lead parts of the leads 7 of the plastic sealed IC are provided at the intermediate parts of the leads 7 and water content is prevented from intruding through the interfaces between the leads 7 and a sealing plastic 8. Moreover, the level of the height in the surface of the wire-bonding pads 3 of the point of each lead and that in the surface of a silicon chip 5 are made in such a way as to become equal to each other to shorten as short as possible the fine wire, and the wire-bonding area of the point part of each lead is made higher than the other part of the lead frame on the side of the semiconductor placing part. By this method, the service life of the lead frame is lengthened in vapor under the prescribed conditions and the reliability of the plastic IC is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はプラスチック封止型工Ｃに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a plastic sealing mold C.

〔従来の技術〕[Conventional technology]

従来のプラスチック封止型工○は、第２図に示すように
、鉄−ニッケル合金、あるいは銅合金を素材としたリー
ドフレーム１のチップボンディング部２およびワイヤー
ボンディング部３に金または銀のメッキ４を施し、チッ
プボンディング部２のメッキ４・上にシリコンチップ５
を塔載したのち、’ｊ　’Ｊ　：ｌ　ンチップ５とリー
ドフレーム１のワイヤーボンディング部３上のメッキ◆
とをファインワイヤー６で接続し、リード７の引出部を
除きこれらを封止プラスチック８で包んで封じたプラス
チック封止型工Ｃが広く用いられている。As shown in Fig. 2, the conventional plastic encapsulation mold ○ has gold or silver plating 4 on the chip bonding part 2 and wire bonding part 3 of the lead frame 1 made of iron-nickel alloy or copper alloy. The silicon chip 5 is placed on the plating 4 of the chip bonding part 2.
After mounting, plating on the wire bonding part 3 of the chip 5 and lead frame 1◆
A plastic sealing mold C is widely used in which the leads 7 are connected with a fine wire 6, and the leads 7 except for the lead-out portion are wrapped and sealed with a sealing plastic 8.

このようなプラスチック封止型ＩＣでは、リードフレー
ムの素材である鉄、−ニッケル合金や鋼合金と、封止材
料であるシリコン樹脂やエポキシ右脂などのプラスチッ
クとの接着性が不充分で、両者の界面からの外界の水分
がパッケージ内に侵入することがあり、水分が°シリコ
ンチップに達すると、ナトリウム、カリウム、塩素など
のイオンと共にシリコンチップそのもの、および電極、
配線な腐食して特性を劣化させるという問題がある。In such plastic-encapsulated ICs, the adhesion between the lead frame material, such as iron, nickel alloy, or steel alloy, and the encapsulating material, which is plastic such as silicone resin or epoxy resin, is insufficient. Moisture from the outside world may enter the package from the interface of
There is a problem that the wiring corrodes and deteriorates its characteristics.

また、最近シリコンチップ５の厚みが大きくなる傾向が
あり、リードフレームのチップボンディング部２とワイ
ヤーボンディング部δの高さが同じの場合、ファインワ
イヤー６とシリコンチップ周辺部９の接触が起りやすく
なっている。それを防止する為にファインワイヤーのル
ープ分大きくとっているが、高価なファインワイヤーを
多く要することによるコストアップと、安定したループ
形状を確保するために必要なファインワイヤーの強度に
限界があるという問題がある。In addition, there is a tendency for the thickness of the silicon chip 5 to increase recently, and if the heights of the chip bonding part 2 and the wire bonding part δ of the lead frame are the same, contact between the fine wire 6 and the silicon chip peripheral part 9 is likely to occur. ing. In order to prevent this, the fine wire loop is made larger, but this increases the cost by requiring a large amount of expensive fine wire, and there is a limit to the strength of the fine wire required to ensure a stable loop shape. There's a problem.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明はリードフレームの形状を改善して上記の問題を
解決することを目的とする。The present invention aims to solve the above problems by improving the shape of the lead frame.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は上記の問題を解決するため、リードフレームの
インナーリード部の中間部分で段差を設け、インナーリ
ード先端部のワイヤーボンディングエリアを、他のリー
ドフレーム部分よりも半導体装置側に高くすることによ
り、リードフレームと封止プラスチックの界面からの水
分侵入を防ぐと共に、シリコンチップ表面との高さレベ
ルが同等になることにより、ファインワイヤーを従来よ
りも短かくすることを可能としたものである。In order to solve the above problem, the present invention provides a step in the middle of the inner lead part of the lead frame, and makes the wire bonding area at the tip of the inner lead higher on the semiconductor device side than the other lead frame parts. This prevents moisture from entering through the interface between the lead frame and the sealing plastic, and also makes it possible to make the fine wire shorter than before by making the height level equal to the silicon chip surface.

段差の位置は、ワイヤーボンディングエリア以外であれ
ば、プラスチック封止エリア内のどこでもよく、段差量
は塔載するシリコンチップの厚さと同等量が好ましい。The position of the step may be anywhere within the plastic sealing area as long as it is not in the wire bonding area, and the amount of step is preferably equivalent to the thickness of the silicon chip to be mounted.

段差の形成方法としては、リードフレーム成形方法とし
て一般的に用いられているスタンピング加工時に、同時
に背なうことが最も実用的である０リードフレーム成形
方法としてフォトエツチング法を使用する場合は、金ま
たは銀メツキ工程とチップボンディング工程の間に、簡
易金型を使用して曲げ加工あるいは絞り加工にて行なう
ことが好ましい。The most practical way to form the step is to turn it back at the same time during the stamping process, which is commonly used as a lead frame forming method.0 When using the photoetching method as the lead frame forming method, gold Alternatively, it is preferable to perform bending or drawing using a simple mold between the silver plating process and the chip bonding process.

〔作用〕[Effect]

第１図に示すように、リード７のインナーリードの中間
部に段差９を設けることにより、リード７と封止プラス
チック８の界面を通しての水分侵入を防止する。又、リ
ード先端のワイヤーボンディング部３とシリコンチップ
５の表面の高さレベルが同等になることにより、コスト
アップと通電不良の原因となるファインワイヤーを極力
短かくすることが可能となる。As shown in FIG. 1, by providing a step 9 in the middle of the inner lead of the lead 7, moisture intrusion through the interface between the lead 7 and the sealing plastic 8 is prevented. Furthermore, since the height level of the wire bonding portion 3 at the tip of the lead and the surface of the silicon chip 5 is made equal, it is possible to make the fine wire as short as possible, which causes cost increase and conduction failure.

〔実施例〕〔Example〕

厚さ０．２５１１ｔｌｌの４２７０イ　（４２重量％Ｎ
ｉ　−Ｆｅ　）　戸−プを精密プレスを用いてインナー
リード中間部ニ０．３０鴎の段差を形成したリードフレ
ーム３作す、このリードフレームのチップボンディング
部およびワイヤーボンディング部に、電気メッキでスポ
ット状に厚さ５μｍの銀のメッキを施した。4270I with a thickness of 0.2511tll (42%N by weight)
i-Fe) Using a precision press, make 3 lead frames with a 0.30 mm step between the inner leads.The chip bonding area and wire bonding area of this lead frame are spot-plated using electroplating. The plate was plated with silver to a thickness of 5 μm.

この後、厚さ０．２５４ｔｍｎのシリコンチップを銀ペ
ーストを用いてチップボンディングを行ない、さらに３
０μｍ径の金線を用いてワイヤーボンディングし、エポ
キシ樹脂でモールドして、エポキシ樹脂封止工Ｃを作成
した。After this, a silicon chip with a thickness of 0.254 tmn was bonded using silver paste, and then
Wire bonding was performed using a gold wire with a diameter of 0 μm, and molding was performed with epoxy resin to create an epoxy resin sealant C.

得られた工Ｃは、従来のインナーリード部に段差を有し
ないリードフレームを用いた工Ｃに比べると、１２５Ｃ
，２気圧の水蒸気中での特性劣化テストにおける寿命が
２倍以上の１５０〜２００時間を示した。又、ワイヤー
ボンディング用金線も、従来に比べると約り０％少なく
て可能となった。The obtained process C is 125C compared to process C using a conventional lead frame without a step in the inner lead part.
In a characteristic deterioration test in water vapor at 2 atm, the lifespan was more than twice that of 150 to 200 hours. Additionally, the amount of gold wire used for wire bonding can now be reduced by approximately 0% compared to conventional methods.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、信頼性が向上し、しがも高価なボンデ
ィングワイヤーの使用量を低減したプラスチック封止型
ＩＣが得られる。According to the present invention, a plastic-sealed IC with improved reliability and reduced usage of expensive bonding wires can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明にががるプラスチック封止型工Ｃの一例
の断面図、第２図は従来のプラスチック封止型工Ｃの断
面図である。 １・・リードフレーム、２・・チップボンディング部、
３・・ワイヤーボンディング部、李・・メッキ、５・・
シリコンチップ、６・・ファインワイヤー、７・・リー
ド、８・・封止プラスチック、９・・インナーリード部
の段差。 出願人　　住友電気工業株式会社 づｌ’ｊ　、ｊ′、、。FIG. 1 is a cross-sectional view of an example of a plastic sealing mold C according to the present invention, and FIG. 2 is a cross-sectional view of a conventional plastic sealing mold C. 1. Lead frame, 2. Chip bonding part,
3... Wire bonding part, Li... Plating, 5...
Silicon chip, 6. Fine wire, 7. Lead, 8. Sealing plastic, 9. Step in inner lead part. Applicant: Sumitomo Electric Industries, Ltd.

Claims (1)

【特許請求の範囲】[Claims] （１）リードフレームのインナーリード部の中間部分で
段差を設け、インナーリード先端部のワイヤーボンディ
ングエリアが他のリードフレーム部分よりも半導体装置
側に高くなつていることを特徴とするプラスチック封止
型ＩＣ。(1) A plastic-sealed type characterized by providing a step in the middle of the inner lead portion of the lead frame so that the wire bonding area at the tip of the inner lead is higher on the semiconductor device side than the other lead frame portions. I.C.
JP59191293A 1984-09-11 1984-09-11 Plastic sealed ic Pending JPS6167929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59191293A JPS6167929A (en) 1984-09-11 1984-09-11 Plastic sealed ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59191293A JPS6167929A (en) 1984-09-11 1984-09-11 Plastic sealed ic

Publications (1)

Publication Number Publication Date
JPS6167929A true JPS6167929A (en) 1986-04-08

Family

ID=16272156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59191293A Pending JPS6167929A (en) 1984-09-11 1984-09-11 Plastic sealed ic

Country Status (1)

Country Link
JP (1) JPS6167929A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563441A (en) * 1992-12-11 1996-10-08 Mitsubishi Denki Kabushiki Kaisha Lead frame assembly including a semiconductor device and a resistance wire

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563441A (en) * 1992-12-11 1996-10-08 Mitsubishi Denki Kabushiki Kaisha Lead frame assembly including a semiconductor device and a resistance wire

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