JPS6167333A - Device for artificially generating delay of signal propagation - Google Patents

Abstract

PURPOSE:To set the variation of artificial delay of signal propagation in a transmitting signal with a small-scale circuit, by inputting a timing signal in a transmitting signal generating circuit by delaying the timing signal by a delaying quantity designated on the basis of time information from the outside. CONSTITUTION:At the control function testing device of a communications satellite, a delaying quantity designating circuit 8 inputs reference time information 7 and a control signal 9 from the outside and a delaying quantity designating signal 10 in a variable delaying circuit 3 in a section in which the delay of transmitting signals is designated by the control signal 9 at each designated time zone. The circuit 3 presets the delaying quantity designated by the signal 10 synchronously to a timing signal 1 and counts down a clock signal 2 as the operating clock of a counter, and then, outputs a signal sending out timing 4 to a transmitting signal generating circuit 5 at the time when the count value is zero. The circuit 5 outputs a transmitting signal to a terminal 6 at the time designated by the delayed timing signal 4 from the circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a circuit that adds a pseudo signal propagation delay to a transmitted signal.

(Conventional O technology) Communication satellites are usually terrestrial 36. It exists OOOkm above the sky and changes its position slightly. For communication equipment such as the TDMA satellite communication system that uses satellites as repeaters, where the signal propagation delay time of the communication system fluctuates, even when maintenance is performed, the signal propagation delay time does not change at all. It is impossible to maintain the same condition, and it is extremely difficult to test the control function of the communication device against fluctuations in signal reception time and the data reception function. Therefore, when signal propagation delay time fluctuates, such as when data is transmitted via a communication satellite repeater, communication equipment Therefore, a test method is required to fully test the control functions of the system. In order to realize the above test, a method can be considered in which a pseudo delay is given to the transmission signal of the local station and then this delayed signal is sent out.

In order to realize the above function according to the prior art, a circuit configuration shown in FIG. 2 has been adopted. In FIG. 2, the conventional signal propagation delay pseudo generator includes a transmission signal generation circuit 22 for generating a transmission signal at a time position specified by the signal transmission timing, and a manual switch for changing the amount by which the total transmission signal is delayed. a delay amount setting circuit 24 for setting and giving instructions, and a delay amount setting circuit 24 for delaying the transmission signal generated by the transmission signal generation circuit 22 by the amount instructed by the output of the delay amount setting circuit 24 and outputting it to the outside. The transmission signal temporary storage circuit 26 was configured.

(Problem to be Solved by the Invention) According to such a circuit, it is not possible to automatically generate a variation in the signal propagation delay time that is added in a pseudo manner, When the amount of delay increases, the circuit scale of the transmission signal temporary storage circuit that includes a shift register or random access memory as a component increases in proportion to the amount of delay, and current consumption also increases significantly. this.

The purpose of the present invention is to input basic time information and control signals from the outside, specify the amount of delay of the transmitted signal in each designated time zone in the section where the control signal instructs the delay of the transmitted signal, and By delaying the signal transmission timing by a specified amount, and inputting the variable delayed signal transmission timing to generate and output the transmission signal at the specified time, all of the above drawbacks are removed and the signal is propagated to the communication system. To provide a complete signal propagation delay simulating generator configured to be able to give a pseudo signal propagation delay variation to a transmitted signal with a small-scale circuit even during maintenance of a communication device where variation in delay time exists. There is a particular thing.

(Means for Solving the Problem) A signal propagation delay pseudo generation device according to the present invention is configured to include a delay amount designation circuit, a variable delay circuit, and a transmission signal generation circuit.

The delay amount designation circuit inputs reference time information and control signals from all external sources, and is used to designate the amount of delay of the transmitted signal in each specified time period in the section where the above control signal instructs the delay of the transmitted signal. be.

The variable delay circuit inputs the output of the delay amount designation circuit and the signal transmission timing, and is designed to delay the signal transmission timing by the amount designated by the output of the delay amount designation circuit.

The transmission signal generation circuit receives the signal transmission timing output from the variable delay circuit, and generates and outputs a transmission signal at a time specified by the signal transmission timing.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a signal propagation delay pseudo generator according to the invention. In FIG. 1, 1 is a timing signal line for instructing the generation of a transmission signal, 2 is a tarok signal line, 6 is a variable delay circuit, 4 is a signal transmission timing signal line, and 10 is a delay amount designation line 18.

The variable delay circuit 6 is constituted by a counter circuit, and the variable delay circuit 6 is composed of a counter circuit, and the variable delay circuit 6 is composed of a counter circuit. The transmission timing signal on signal line 1, the clock signal on signal line 2, and the delay amount designation signal on signal line 10 are input, and in synchronization with the timing signal on signal line 1, the signal is specified by the delay amount designation signal. After presetting the value, the clock signal on signal line 2 is used as the operating clock for the above counter to execute a countdown, and the signal transmission timing is set on all signal lines 4 at the time when the value of the content of the counter is zero. This is what is output.

On the other hand, 7 is an input signal line for the reference time information signal, 8 is a delay amount designation circuit configured with a read-only memory, and 9 is a control for determining whether or not to generate a pseudo variation in the signal propagation delay amount. The delay amount specifying circuit 8, which is constituted by six read-only memories that are signal lines, receives the reference time information signal on the signal line Z as a ROM address, and the control signal on the signal line 9 determines the amount of signal propagation delay. When full variation is specified, a delay amount designation signal is output onto the signal line 10 as the contents of the read-only memory corresponding to the designated address. When the tOΔ1 address specified by the reference time information signal on the signal line Z changes (by changing the direction), a delay amount designation signal corresponding to each changed address is transmitted from the delay amount designation circuit 8 onto the signal line 10. Output.

Therefore, by writing and setting the same group total delay amount specifying circuit 8 corresponding to each address of the read-only memory, the R Oh-1 address determined by the reference time information signal on the signal line 7 is set. Correspondingly, each delay amount can be fully read out. Therefore, depending on the ROM address, each group η
It is possible to easily change the amount of continuous transmission of the transmitted signal during the time period. Furthermore, by setting the rate of change of each reference time from the outside, it is possible to freely set the rate of change of the delay amount designation signal on the signal line 10, that is, the rate of change of the signal propagation delay that occurs in a pseudo manner. is possible. Transmission signal generation circuit 5 Inputs the signal transmission timing outputted from the fd variable delay circuit 3 via the signal line 4, generates a transmission signal at the timing specified by this timing, and outputs the transmission signal onto the signal line 6. Send all of this as .

(Effects of the Invention) As explained above, according to the present invention, the timing 1 word is output after being delayed by a specified time (C), and the time (C) that is not supplied from outside is also As a result, the signal generation timing is delayed by specifying the entire delay amount of the timing signal in each time period (from C, ↓ (To summarize, the signal propagation delay is generated in a small circuit similar to a gold wedge,
This has the advantage that fluctuations in the amount of signal propagation delay can also be freely set.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a signal propagation delay pseudo generator according to the present invention. FIG. 2 is a block diagram showing a modified example of a conventional signal propagation delay pseudo generator. 3...-Variable delay circuit 5.22ψ...Transmission signal generation circuit 8...Delay amount specification circuit 24...Delay amount specification circuit 26...Transmission signal temporary storage circuit 1.2j4, 6, 7, 9 , 10, 21, 2M.

Claims (1)

[Claims] a delay amount designation circuit for inputting reference time information and a control signal from the outside, and for designating a delay amount of the transmission signal in each specified time period in a section where the control signal instructs a delay of the transmission signal; a variable delay circuit for inputting the output of the delay amount designation circuit and the signal transmission timing and delaying the signal transmission timing by an amount designated by the output of the delay amount designation circuit; and a transmission signal generation circuit for inputting the signal transmission timing and generating and outputting a transmission signal at a time specified by the signal transmission timing. Pseudo generator.