JPS6164763U - - Google Patents
Info
- Publication number
- JPS6164763U JPS6164763U JP15041484U JP15041484U JPS6164763U JP S6164763 U JPS6164763 U JP S6164763U JP 15041484 U JP15041484 U JP 15041484U JP 15041484 U JP15041484 U JP 15041484U JP S6164763 U JPS6164763 U JP S6164763U
- Authority
- JP
- Japan
- Prior art keywords
- reception
- frequency
- detection circuit
- reception level
- receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Landscapes
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
Description
第１図は本考案の一実施例を説明するためのブ
ロツク図、第２図は第１図における選局制御フロ
ーチヤート、第３図は本考案における選局動作を
説明するための周波数スペクトル、第４図は従来
のチユーナを示すブロツク図である。
１…アンテナ、２…フロントエンド、３…中間
周波数増幅回路、４…選局回路、５Ａ…選局回路
本体、５Ｂ…受信レベル検出回路、５Ｃ…選局調
整指令スイツチ。
FIG. 1 is a block diagram for explaining an embodiment of the present invention, FIG. 2 is a channel selection control flowchart in FIG. 1, and FIG. 3 is a frequency spectrum for explaining the channel selection operation in the present invention. FIG. 4 is a block diagram showing a conventional tuner. 1...Antenna, 2...Front end, 3...Intermediate frequency amplification circuit, 4...Tuning selection circuit, 5A...Tuning selection circuit main body, 5B...Reception level detection circuit, 5C...Tuning adjustment command switch.
Claims (1)
において、受信状態の受信レベルを検出する受信
レベル検出回路と、受信周波数ｆｏとこの受信周
波数ｆｏから中間周波数ｆｉの２倍の周波数分ず
らした受信周波数ｆ１に切換え制御し、両受信周
波数ｆｏおよびｆ１における前記検出回路の検出
受信レベルのうち該受信レベルが大きい方の受信
周波数に切換え設定する選局回路本体とを備えた
ことを特徴とするチユーナの選局回路。 In a tuner that receives data using the superheterodyne system, there is a reception level detection circuit that detects the reception level in the reception state, and a reception frequency fo and switching control to a reception frequency f1 that is shifted by twice the intermediate frequency fi from the reception frequency fo. and a tuning circuit main body that switches and sets the receiving frequency to whichever reception level is higher among the reception levels detected by the detection circuit at both receiving frequencies fo and f1 . .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15041484U JPS6164763U (en) | 1984-10-04 | 1984-10-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15041484U JPS6164763U (en) | 1984-10-04 | 1984-10-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6164763U true JPS6164763U (en) | 1986-05-02 |
Family
ID=30708559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15041484U Pending JPS6164763U (en) | 1984-10-04 | 1984-10-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6164763U (en) |
-
1984
- 1984-10-04 JP JP15041484U patent/JPS6164763U/ja active Pending
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