JPS6162485U - - Google Patents

Info

Publication number
JPS6162485U
JPS6162485U JP14818784U JP14818784U JPS6162485U JP S6162485 U JPS6162485 U JP S6162485U JP 14818784 U JP14818784 U JP 14818784U JP 14818784 U JP14818784 U JP 14818784U JP S6162485 U JPS6162485 U JP S6162485U
Authority
JP
Japan
Prior art keywords
pulse
circuit
keying
video
generates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14818784U
Other languages
Japanese (ja)
Other versions
JPH0510472Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984148187U priority Critical patent/JPH0510472Y2/ja
Publication of JPS6162485U publication Critical patent/JPS6162485U/ja
Application granted granted Critical
Publication of JPH0510472Y2 publication Critical patent/JPH0510472Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Television Receiver Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のVTR用中間周波
処理回路の概略を示すブロツク図、第2図は本考
案の特徴となるキーイングパルス発生回路の具体
的な回路図、第3図は第2図各部の波形図である
。 1…チユーナ、2…IF処理回路、3…音声処
理回路、4…映像受信回路、5…4.5MHz検
波回路、6…音声IF増幅回路、7…FM検波回
路、8…低周波増幅回路、9…映像IF増幅回路
、10…映像検波回路、11…映像増幅回路、1
2…キードAGC回路、20…キーイングパルス
発生回路、21…同期パルス発生器、22…パル
ス整形器。
FIG. 1 is a block diagram schematically showing an intermediate frequency processing circuit for a VTR according to an embodiment of the present invention, FIG. 2 is a specific circuit diagram of a keying pulse generation circuit which is a feature of the present invention, and FIG. FIG. 2 is a waveform diagram of each part. DESCRIPTION OF SYMBOLS 1... tuner, 2... IF processing circuit, 3... audio processing circuit, 4... video receiving circuit, 5... 4.5MHz detection circuit, 6... audio IF amplification circuit, 7... FM detection circuit, 8... low frequency amplification circuit, 9...Video IF amplification circuit, 10...Video detection circuit, 11...Video amplification circuit, 1
2... Keyed AGC circuit, 20... Keying pulse generation circuit, 21... Synchronous pulse generator, 22... Pulse shaper.

Claims (1)

【実用新案登録請求の範囲】 少なくとも映像IF増幅回路と、入力信号レベ
ルの変化に応じてチユーナおよび/または映像I
F増幅回路の利得を制御するためのキードAGC
回路と、キードAGC回路をキーオンさせるため
のキーイングパルスを発生するキーイングパルス
発生回路とを含み、 前記キーイングパルス発生回路は、複合映像信
号から水平同期信号に同期したパルスを発生する
同期パルス発生器と、同期パルスをキーイングパ
ルスに必要な時定数のパルスに整形してキーイン
グパルスを導出するパルス整形器を備えたことを
特徴とするVTR用IF処理回路。
[Claims for Utility Model Registration] At least a video IF amplifier circuit, a tuner and/or a video I
Keyed AGC for controlling the gain of the F amplifier circuit
circuit, and a keying pulse generation circuit that generates a keying pulse for keying on a keyed AGC circuit, and the keying pulse generation circuit includes a synchronization pulse generator that generates a pulse synchronized with a horizontal synchronization signal from a composite video signal. An IF processing circuit for a VTR, comprising a pulse shaper that shapes a synchronizing pulse into a pulse having a time constant necessary for a keying pulse to derive a keying pulse.
JP1984148187U 1984-09-28 1984-09-28 Expired - Lifetime JPH0510472Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984148187U JPH0510472Y2 (en) 1984-09-28 1984-09-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984148187U JPH0510472Y2 (en) 1984-09-28 1984-09-28

Publications (2)

Publication Number Publication Date
JPS6162485U true JPS6162485U (en) 1986-04-26
JPH0510472Y2 JPH0510472Y2 (en) 1993-03-15

Family

ID=30706405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984148187U Expired - Lifetime JPH0510472Y2 (en) 1984-09-28 1984-09-28

Country Status (1)

Country Link
JP (1) JPH0510472Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50110128U (en) * 1974-02-19 1975-09-09

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50110128U (en) * 1974-02-19 1975-09-09

Also Published As

Publication number Publication date
JPH0510472Y2 (en) 1993-03-15

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