JPS6161554A - Signal control device - Google Patents

Abstract

PURPOSE:To make possible the processing of a large capacity signal traffic by connecting a plural processor serially and processing them with a function partition. CONSTITUTION:A line control device CSE101 performs the signal identification by a signal flag received from a line and a check by a error inspection cord before it takes out a significant signal only. A retransmission control at a sequence error is performed by an error control signal. Furthermore, it stores a signal, which is identified by a signal length display signal to be sent to the host in a buffer. A distribution and aggregation control device XIP102 scans all CSE sequently and sends a significant signal to a fetch signal network control device NCP103. The NCP uses the signal in the NCP when the identification of the received signal is common line signal network control information and sends to a data interface control device DIP104 when it is a call control signal. The DIP converts the received signal into a signal format in an exchange and into terminal number information and sends to the exchange processor CP107 through an interface control device IIP105.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a common line signal control device for an electronic converter that handles the Na3 signaling system recommended by the VA Telegraph and Telegraph Consultative Committee (CCITT).

[Background of the invention]

The common line signaling system is a system in which call control signals between exchanges are sent and received in packet-type signal units. Therefore, it is necessary to perform signal error control, routing, flow control, etc. For this reason, since the processor requires many processing steps for signal unit processing, the switching equipment needs to have a capacity for this in advance, or it is necessary to use a separate processor or the like to perform the processing. In particular, when handling a large amount of signal traffic, such as at a signal relay station, a large-capacity processor is required.

[Purpose of the invention]

An object of the present invention is to provide a configuration for processing a large amount of signal traffic in a common line signal control device in an exchange.

[Summary of the invention]

To this end, the present invention expands the processing capacity of the system by using a plurality of processors and processing them in a divided manner. Furthermore, it is characterized by considering the lv layer configuration and functional layering up to communication with the exchange according to the communication procedure of the N13 signaling system, and connecting processors in series according to the signal flow.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a common line signal control device in an electronic exchange according to the present invention.

Here, 101 is provided for link support for common line signals, and performs common line signal unit identification, error detection, error correction by Neekens number control, signal error rate monitoring, etc.
Line control bag fi that performs the level 2 function of the signaling system
(C3E), 102 collects the signal units from each C3EIOI and sends the upper unit to each C3E 101
Distribution aggregation control equipment E (XIP) for distribution to 10
3 is N13, which relays the signal unit to the upper processor, relays between circuits, and performs flow control, routing, etc.
Signaling network controller (
NCP).

A data interface controller (DIP) 104 changes the signal unit processed by the NCP 103 into a data format used in the exchange.

Reference numeral 105 denotes an internal interface control device CIIP that controls connection to the system communication bus 106, communicates with exchange processing processors, etc., and also manages the operating status of each of the above-mentioned control devices. 107 is an exchange processing processor (
CP1 to CPm) and 108 are maintenance and operation processors.

FIG. 2 is a diagram showing an example of the format of a signal unit in each control device. Here, 2C) 1 is a flag (No. 1 F, 202 is an error control signal EC1203 is a signal length display signal LI, 204 is a signal length display signal 5IO1205
is the signal S of the user part (level 4) using the Na3 signal
I F 206 it.

Departure/destination address signal LABEL included in SIF, 207
is the error detection code GK. :j! 208 is an address corresponding to LABEL within the exchange.

Next, referring to Figures 1 and 2, the operation will be described. The signal from line 0 is in the format shown in Figure 2 (a), and is C3E 10.
1 is received. In C3E101, after performing signal identification using flag 201 and checking using error check code CK2O7, only valid signals are extracted, and temporary retransmission control for sequence errors is performed using error control signal EC202 based on sequence number check.Furthermore, signal length display signal L
I203 identifies whether the signal is to be used in the C3E101 or the signal to be sent to the upper level, and if the signal is to be sent to the higher level, the 0 distribution aggregation control unit stores the contents shown in FIG. 2(b) in the buffer to be sent to the higher level. ! XIP102 sequentially scans all CSEs, takes in moving signals, and transmits signals to the signal network controller [NCP
The data is stored in a buffer for sending to 103. NCP103
Then, the buffer reads the signal and identifies the 5IO 204 and uses it in the NCP 103 for common line signal network control information.

In the case of a call control signal, it is stored in a buffer to be sent to the DIP 104. The DIP 104 reads the signal from the buffer, converts the signal format into the signal format within the exchange, and converts it into terminal number information PN 208 within the information exchange of LABEL 206, and sends the signal to the corresponding subscriber,
Terminals such as trunks.

Included exchange processing processors CPI to CPm107
The internal interface controller I
It is sent to the interface buffer with IP105. IIP
At 105, this signal is taken out from the buffer and sent to bus 106.
Via, send to the corresponding CP107.

The above describes the case of reception, but the above also applies to transmission.
Perform the opposite flow of Iroh processing.

In the case of a signal relay station, the NCP 103 performs routing control and sends the signal to another line.

In order to perform the above processing, the transmitting side device of the signal unit,
A shared memory that can be accessed by both devices is provided between the devices on the receiving side of the signal, and signal units are transferred between the devices via the memory.

〔Effect of the invention〕

According to the present invention, the CCITT recommendation, Na3 signaling system is followed. In a common line signaling device, a processor having functions according to the functional division of the Na3 signaling system.

By connecting in series a plurality of processors each having a switch interface function, it is possible to configure a station with a large amount of signal traffic, such as a signal relay station.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a connection configuration of a common line signal control device according to the present invention, and FIG. 2 is a diagram showing a signal format 1-. 101...Line control device, 102...Distribution and aggregation control device, 103...Signal network control device, 104...Data interface control device, 105...Internal interface control device, 107... Exchange processing processor. 201...Flag, 202...Error control No. 46, 2
03...Signal identification display signal, 205...User section signal.

Claims (1)

[Claims] Sends and receives signal units to the line, identifies signal units using flags, detects errors using error check codes,
a microprocessor-controlled line control device that performs error correction using sequence number control and error rate monitoring;
a distribution and aggregation control device that distributes and aggregates signal units to a plurality of devices, and a signal unit that performs routing control for relaying the signal units to an exchange processing processor or within a line according to the contents of the signal units; a signal network control device that controls the flow rate of the signal; a data interface control device that converts the data format of the signal unit between the signal network control device and the exchange processor; The controller controls the system communication bus, communicates with the exchange processor, and manages the operating status of each of the above-mentioned control devices, and each of the above-mentioned devices are connected by a shared memory. A signal control device characterized by: