JPS6161476U - - Google Patents
Info
- Publication number
- JPS6161476U JPS6161476U JP14573684U JP14573684U JPS6161476U JP S6161476 U JPS6161476 U JP S6161476U JP 14573684 U JP14573684 U JP 14573684U JP 14573684 U JP14573684 U JP 14573684U JP S6161476 U JPS6161476 U JP S6161476U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- voltage
- supplied
- series
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案の一実施例に係る表示装置の構
成図、第２図は本考案の表示装置における表示素
子の点灯状態を示す特性図、第３図は従来の表示
装置の構成図である。
Ｃ１〜Ｃｎ…比較器、Ｄ１〜Ｄｎ…表示素子、
ＲＡ，ＲＢ…抵抗器、Ｒ１〜Ｒｎ−１…直列接続
抵抗器群、Ｖｉｎ…入力電圧、Ｖｍａｘ…最小基
準電圧、Ｖｒ…接続点電圧、Ｖ１〜Ｖｎ…基準電
圧。
FIG. 1 is a block diagram of a display device according to an embodiment of the present invention, FIG. 2 is a characteristic diagram showing lighting states of display elements in the display device of the present invention, and FIG. 3 is a block diagram of a conventional display device. be. C1 to Cn... comparators, D1 to Dn... display elements,
RA, RB...Resistor, R1-Rn-1...Series connected resistor group, Vin...Input voltage, Vmax...Minimum reference voltage, Vr...Connection point voltage, V1-Vn...Reference voltage.
Claims (1)
の基準電圧が供給される第２の入力端子と、前記
第１の基準電圧の電圧値よりも低い電圧値を有す
る第２の基準電圧が供給される第３の入力端子と
、前記第１の入力端子と第２の入力端子間に接続
される直列接続された第１、第２の抵抗器と、第
１第２の抵抗器の接続点と前記第３の入力端子間
に接続される複数の抵抗値の等しい抵抗器を直列
接続してなる直列抵抗器群と、この直列抵抗群に
印加される電圧を該直列抵抗群の各抵抗器により
分割して得られる複数の基準電圧の各々に対応し
て該基準電圧と前記入力電圧とを入力して比較す
る複数の比較手段と、これら比較手段の各々に対
応して該比較手段の出力が供給される複数の表示
素子とを備えることを特徴とする表示装置。 a first input terminal to which an input voltage is supplied;
a second input terminal to which a reference voltage is supplied; a third input terminal to which a second reference voltage having a voltage value lower than the voltage value of the first reference voltage is supplied; first and second resistors connected in series between the input terminal and the second input terminal; and a plurality of resistors connected between the connection point of the first and second resistors and the third input terminal. A series resistor group formed by connecting resistors with equal resistance values in series, and a plurality of reference voltages obtained by dividing the voltage applied to this series resistor group by each resistor of the series resistor group. A plurality of comparison means for inputting and comparing the reference voltage and the input voltage correspondingly, and a plurality of display elements to which the output of the comparison means is supplied corresponding to each of the comparison means. Characteristic display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14573684U JPS6161476U (en) | 1984-09-28 | 1984-09-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14573684U JPS6161476U (en) | 1984-09-28 | 1984-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6161476U true JPS6161476U (en) | 1986-04-25 |
Family
ID=30703993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14573684U Pending JPS6161476U (en) | 1984-09-28 | 1984-09-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6161476U (en) |
-
1984
- 1984-09-28 JP JP14573684U patent/JPS6161476U/ja active Pending
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