JPS6161324B2 - - Google Patents

Info

Publication number
JPS6161324B2
JPS6161324B2 JP55040434A JP4043480A JPS6161324B2 JP S6161324 B2 JPS6161324 B2 JP S6161324B2 JP 55040434 A JP55040434 A JP 55040434A JP 4043480 A JP4043480 A JP 4043480A JP S6161324 B2 JPS6161324 B2 JP S6161324B2
Authority
JP
Japan
Prior art keywords
signal
digital signal
digital
center value
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55040434A
Other languages
Japanese (ja)
Other versions
JPS56137211A (en
Inventor
Masahito Norita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP4043480A priority Critical patent/JPS56137211A/en
Publication of JPS56137211A publication Critical patent/JPS56137211A/en
Publication of JPS6161324B2 publication Critical patent/JPS6161324B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01DMEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D3/00Indicating or recording apparatus with provision for the special purposes referred to in the subgroups
    • G01D3/02Indicating or recording apparatus with provision for the special purposes referred to in the subgroups with provision for altering or correcting the law of variation

Description

【発明の詳細な説明】 例えばデジタル電圧計で測定された複数桁のデ
ジタル信号をデジタル・アナログ変換器でアナロ
グ量の電圧に変換し、これをアナログ信号の自動
記録計で記録する場合に、従来は単に下位の桁を
切捨て、例えば上位3桁をアナログ信号に変換す
ることにより記録計に直接加えていた。このため
例えば0800000μVから1400000μVの範囲で変化
するデジタル信号につき、上位3桁をアナログ信
号に変換して記録計に加えると、その入力は080
〜140となるから、記録紙のフルスケールを1000
とすると記録図形は第1図aに曲線pで示したよ
うになる。従つて紙面の利用率が極めて悪く、記
録の精度が充分でない。また第4〜6桁をアナロ
グ信号に変換すると記録計の入力信号は800〜
1000および0〜400となるから、その記録図形は
同図に曲線p′で示したように不連続部を生じて、
読み誤り等のおそれがある。更に入力デジタル信
号が例えば−200000μVから+500000μVの範囲
で変化する場合に、これを上述のような記録計に
加えて絶対値を記録すると、第1図bに曲線qで
示したような図形が記録されるから、極性の反転
部分について誤観測を生じ易い。従つて本発明
は、デジタル信号をアナログ記録計で記録する場
合において上述のような欠点を除去しようとする
ものである。
Detailed Description of the Invention For example, when converting a multi-digit digital signal measured with a digital voltmeter into an analog voltage using a digital-to-analog converter and recording this using an automatic analog signal recorder, conventional simply truncated the lower digits, converted the upper 3 digits into analog signals, and added them directly to the recorder. Therefore, for example, if the upper three digits of a digital signal that varies in the range of 0800000μV to 1400000μV are converted to an analog signal and applied to a recorder, the input will be 080000μV to 1400000μV.
~140, so the full scale of the recording paper is 1000
In this case, the recorded figure will be as shown by the curve p in FIG. 1a. Therefore, the utilization of paper space is extremely poor, and the accuracy of recording is not sufficient. Also, if the 4th to 6th digits are converted to analog signals, the input signal of the recorder will be 800~
1000 and 0 to 400, the recorded figure will have a discontinuous part as shown by the curve p' in the same figure,
There is a risk of misreading. Furthermore, when the input digital signal changes in the range of, for example, -200,000 μV to +500,000 μV, if this is added to the recorder described above and the absolute value is recorded, a figure like the one shown by curve q in Figure 1 b will be recorded. Therefore, it is easy to make erroneous observations about the polarity reversal portion. Therefore, the present invention seeks to eliminate the above-mentioned drawbacks when recording digital signals with an analog recorder.

第2図は本発明の装置の構成を示した図で、記
録しようとする任意のデジタル信号Xおよびその
極性の正負を示す信号をそれぞれ端子TおよびP
に加える。また上記デジタル信号が変化すると予
想される範囲の中心値Yを中心値設定器Sに設定
すると共にアナログ記録器Rにおける記録面の中
心値に相当するデジタル信号Zを端子Qに加えて
おく。デジタル演算器Cはこれらの入力信号につ
いて(±X−Y+Z)の演算を行い、その演算結
果をデジタルアナログ変換器DAに加えて、その
出力をアナログ記録器Rで記録する。
FIG. 2 is a diagram showing the configuration of the apparatus of the present invention, in which an arbitrary digital signal X to be recorded and a signal indicating its polarity are connected to terminals T and P, respectively.
Add to. Further, the center value Y of the range in which the digital signal is expected to change is set in the center value setter S, and a digital signal Z corresponding to the center value of the recording surface of the analog recorder R is applied to the terminal Q. Digital calculator C performs calculations (±X-Y+Z) on these input signals, applies the calculation results to digital-to-analog converter DA, and records the output with analog recorder R.

すなわち記録しようとするデジタル信号Xの予
想される変化範囲を例えば前述のように800000〜
1400000とし、下3桁を切捨ると設定器Sに設定
される中心値Yは1100である。また記録器Rにお
ける記録面の中心値に相当するデジタル信号Zを
500とすると、演算器Cから送出されるデジタル
信号の予想最小値が200、最大値が800となる。従
つて記録器Rには第1図aに曲線vで示したよう
に、記録面全面を有効に利用して高精度で、しか
も連続した1本の曲線が記録される。
In other words, the expected change range of the digital signal X to be recorded is, for example, 800000~
If the value is 1400000 and the last three digits are rounded down, the center value Y set in the setting device S is 1100. In addition, the digital signal Z corresponding to the center value of the recording surface in the recorder R is
If it is 500, the expected minimum value of the digital signal sent from the arithmetic unit C will be 200, and the expected maximum value will be 800. Therefore, as shown by the curve v in FIG. 1a, the recorder R records a single continuous curve with high precision by effectively utilizing the entire recording surface.

また記録しようとするデジタル信号Xが例えば
−200000から+500000の間で変化するものと予想
される場合に、その上位3桁をとると設定器Sに
設定される中心値Yは+150となる。また端子Q
にはアナログ記録面の中心値、従つて前述の場合
と同様に500に相当するデジタル信号Zを加え
る。演算器Cはこれらの値について(±X−Y+
Z)の演算を行うから、その出力信号の最小値は
+150最大値は850となる。従つてアナログ記録計
Rには第1図bに曲線wで示したように+150か
ら+850の間で変化する1本の連続した曲線が画
かれる。このように入力デジタル信号が正負に亘
つて変化する場合でも記録された曲線wには曲線
qのような不連続点を生じないから、高精度でし
かも続取りの容易なアナログ記録を行うことがで
きる。
Further, when the digital signal X to be recorded is expected to vary between, for example, -200000 to +500000, the center value Y set in the setting device S will be +150 if the upper three digits are taken. Also terminal Q
is the center value of the analog recording surface, and thus a digital signal Z corresponding to 500 is added as in the previous case. Arithmetic unit C calculates (±X-Y+
Z), the minimum value of the output signal is +150 and the maximum value is 850. Therefore, one continuous curve is drawn on the analog recorder R, which varies between +150 and +850, as shown by the curve w in FIG. 1b. In this way, even when the input digital signal changes between positive and negative, discontinuous points like curve q do not occur in the recorded curve w, so it is possible to perform analog recording with high precision and easy continuity. can.

第3図は上述のような原理にもとづく、本発明
の具体的実施例の構成を示した図で、端子t1,
t2………t9に記録しようとする9桁のデジタ
ル信号の各桁が加えられる。選択スイツチGはこ
のデジタル入力信号のうち記録すべき適宜の3桁
を選定してラツチ回路L1,L2,L3に加え、
また端子Pの極性信号はラツチ回路L4に加えら
れる。これらのラツチ回路は端子Vのストローブ
信号により、前記各端子の信号を捕捉してマルチ
プレクサM1,M2,M3に加える。かつラツチ
回路L1,L2,L3の出力は補数回路H1,H
2,H3を介して、上記マルチプレクサに加わ
る。補数回路H1,H2はそれらの下位の桁が0
のとき10の補数を送出して0以外のとき9の補数
を送出し、H3は常に10の補数を送出する。また
マルチプレクサM1,M2,M3はラツチ回路L
4から加えられる極性信号が正のときはラツチ回
路から直接加えられる信号を送出し、負のときは
上述の補数を送出して、加算回路A2またはデジ
タル・アナログ変換器DAの下位の桁に加える。
従つて入力信号用補数回路H1,H2,H3はn
桁の入力信号が負の場合において、これに10n+1
を加算した値を送出する。
FIG. 3 is a diagram showing the configuration of a specific embodiment of the present invention based on the above-mentioned principle, in which the terminals t1,
Each digit of the 9-digit digital signal to be recorded is added to t2...t9. The selection switch G selects appropriate three digits to be recorded from this digital input signal and adds them to the latch circuits L1, L2, L3.
The polarity signal at terminal P is also applied to latch circuit L4. These latch circuits capture the signals at the respective terminals according to the strobe signal at terminal V and apply them to multiplexers M1, M2, and M3. And the outputs of latch circuits L1, L2, L3 are complement circuits H1, H
2, to the multiplexer via H3. Complement circuits H1 and H2 have their lower digits 0.
When , it sends out 10's complement, and when it is other than 0, it sends out 9's complement, and H3 always sends out 10's complement. Also, multiplexers M1, M2, M3 are latch circuits L
When the polarity signal added from 4 is positive, it sends out the signal that is directly added from the latch circuit, and when it is negative, it sends out the complement mentioned above and adds it to the lower digit of adder circuit A2 or digital-to-analog converter DA. .
Therefore, the input signal complement circuits H1, H2, H3 are n
If the digit input signal is negative, add 10 n+1 to this
Sends the added value.

更に第3図の中心値設定器Sには前記端子t
1,t2………に加えられる信号について予想さ
れる変化範囲のほぼ中心に相当する例えば1桁の
信号およびその極性を設定する。この信号が直接
または中心値設定用補数回路H5を介してマルチ
プレクサM4に加わるが、補数回路H5は信号が
負のときにその桁数をmとすると、信号に10m+1
を加えた補数を送出し、マルチプレクサM4は信
号の正負に応じて設定器Sに設定された値または
上記補数を加算回路A1に加える。また端子Qに
は記録面の中心値に相当する1桁のデジタル信
号、すなわち第1図のような記録面の場合は数値
5を示す信号を加える。従つて加算回路A1にお
いては、前述の(−Y+Z)/100の演算が行わ
れる。その出力がマルチプレクサM1の出力信号
と共に加算回路A2に加わるから、前記3桁の入
力信号の最高位の桁の値をxとすると該加算回路
A2においては{x+(−Y+Z)}/100の演算
が行われる。この加算回路A2の出力信号が2進
符号を10進符号に変換するコード変換回路Bを介
してデジタル・アナログ変換器DAの最上位の桁
に加わる。かつこの変換器には、下位の桁にマル
チプレクサM2,M3の出力信号が加つているか
ら、該変換器から(X−Y+Z)に相当するアナ
ログ信号が送出されて記録器Rで記録される。
Furthermore, the center value setter S in FIG.
For example, a one-digit signal and its polarity corresponding to approximately the center of the expected change range for the signal added to t2, t2, etc. are set. This signal is applied directly or via the center value setting complement circuit H5 to the multiplexer M4, but when the signal is negative, the complement circuit H5 inputs 10 m+1 signals when the number of digits is m.
The multiplexer M4 adds the value set in the setter S or the complement to the adder circuit A1 depending on whether the signal is positive or negative. Further, a one-digit digital signal corresponding to the center value of the recording surface, that is, a signal indicating the numerical value 5 in the case of a recording surface as shown in FIG. 1, is applied to the terminal Q. Therefore, in the adder circuit A1, the above-mentioned calculation of (-Y+Z)/100 is performed. Since its output is applied to the adder circuit A2 along with the output signal of the multiplexer M1, if the value of the highest digit of the three-digit input signal is x, the adder circuit A2 performs the calculation of {x+(-Y+Z)}/100. will be held. The output signal of this adder circuit A2 is applied to the most significant digit of the digital-to-analog converter DA via a code conversion circuit B that converts a binary code into a decimal code. Moreover, since the output signals of multiplexers M2 and M3 are added to the lower digits of this converter, an analog signal corresponding to (X-Y+Z) is sent out from the converter and recorded by the recorder R.

以上説明したように本発明の装置は、記録しよ
うとする複数桁のデジタル信号における上位の桁
に変化を生じた場合、あるいは極性に変化を生じ
た場合でも記録曲線に不連続点を生ずることな
く、これを1本の連続した曲線として記録するこ
とができる。従つて読み取りが容易であると共に
記録紙の全面を有効に利用して高精度の記録を行
い得るものである。
As explained above, the device of the present invention does not cause discontinuities in the recording curve even when there is a change in the upper digits of a multi-digit digital signal to be recorded or when there is a change in polarity. , which can be recorded as one continuous curve. Therefore, it is easy to read, and the entire surface of the recording paper can be effectively used to perform high-precision recording.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はアナログ記録曲線の一例を示した図、
第2図は本発明の装置の構成を示した図、また第
3図は本発明の具体的実施例の構成図である。な
お図において、Tは記録しようとするデジタル信
号の入力端子、Pはその極性を示す信号の入力端
子、Qは記録面の中心の値に相当するデジタル信
号の入力端子、Sは中心値設定器、Cは演算器、
DAはデジタル・アナログ変換器、Rはアナログ
記録器、H1,H2,H3は入力信号用補数回
路、M1,M2,M3は入力信号用マルチプレク
サ、H5は中心値設定用補数回路、M4は中心値
設定用マルチプレクサ、A1,A2は加算回路で
ある。
Figure 1 shows an example of an analog recording curve.
FIG. 2 is a diagram showing the configuration of an apparatus according to the present invention, and FIG. 3 is a diagram showing the configuration of a specific embodiment of the present invention. In the figure, T is the input terminal for the digital signal to be recorded, P is the input terminal for the signal indicating its polarity, Q is the input terminal for the digital signal corresponding to the value at the center of the recording surface, and S is the center value setting device. , C is an arithmetic unit,
DA is a digital-to-analog converter, R is an analog recorder, H1, H2, H3 are input signal complement circuits, M1, M2, M3 are input signal multiplexers, H5 is a center value setting complement circuit, M4 is a center value The setting multiplexers A1 and A2 are adder circuits.

Claims (1)

【特許請求の範囲】[Claims] 1 n桁の入力デジタル信号が負の場合において
これに10n+1を加算した値を送出する入力信号用
補数回路と、上記入力デジタル信号が正のときは
その入力デジタル信号を送出するが負のときは上
記補数回路の出力デジタル信号を送出する入力信
号用マルチプレクサと、上記入力デジタル信号に
ついて予想される変化範囲の中心値を設定する中
心値設定器と、この中心値設定器に設定されたm
桁のデジタル信号が負の場合においてこれに
10m+1を加算した値を送出する中心値設定信号用
補数回路と、前記中心値設定器に設定されたデジ
タル信号の正負に応じてそれぞれこのデジタル信
号自体または上記中心値設定信号用補数回路の出
力デジタル信号を送出する中心値設定信号用マル
チプレクサと、前記入力信号用マルチプレクサの
出力デジタル信号から上記中心値設定信号用マル
チプレクサの出力デジタル信号を差し引くと共に
記録面の中心値に相当したデジタル信号を加算す
るデジタル演算器と、上記デジタル演算器の出力
信号をアナログ信号に変換するデジタル・アナロ
グ変換器と、上記デジタル・アナログ変換器の出
力信号を記録するアナログ記録器とよりなること
を特徴とするデジタル信号のアナログ記録装置。
1 An input signal complement circuit that sends out the value obtained by adding 10 n+1 to the input digital signal of n digits when it is negative, and when the input digital signal is positive, it sends out the input digital signal, but it is negative. In this case, an input signal multiplexer that sends out the output digital signal of the complement circuit, a center value setter that sets the center value of the expected change range for the input digital signal, and a center value setter that sets the center value of the expected change range for the input digital signal, and m
This applies when the digital signal of the digit is negative.
A complement circuit for the center value setting signal that sends out the value obtained by adding 10 m+1 , and a complement circuit for the digital signal itself or the center value setting signal, respectively, depending on the positive or negative of the digital signal set in the center value setter. subtract the output digital signal of the center value setting signal multiplexer from the output digital signal of the input signal multiplexer, and generate a digital signal corresponding to the center value of the recording surface. It is characterized by comprising a digital arithmetic unit that performs addition, a digital-analog converter that converts the output signal of the digital arithmetic unit into an analog signal, and an analog recorder that records the output signal of the digital-analog converter. Analog recording device for digital signals.
JP4043480A 1980-03-31 1980-03-31 Analog recording device for digital signal Granted JPS56137211A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4043480A JPS56137211A (en) 1980-03-31 1980-03-31 Analog recording device for digital signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4043480A JPS56137211A (en) 1980-03-31 1980-03-31 Analog recording device for digital signal

Publications (2)

Publication Number Publication Date
JPS56137211A JPS56137211A (en) 1981-10-27
JPS6161324B2 true JPS6161324B2 (en) 1986-12-25

Family

ID=12580527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4043480A Granted JPS56137211A (en) 1980-03-31 1980-03-31 Analog recording device for digital signal

Country Status (1)

Country Link
JP (1) JPS56137211A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120813A (en) * 1984-07-07 1986-01-29 Nippon Denso Co Ltd Measuring instrument for vehicle

Also Published As

Publication number Publication date
JPS56137211A (en) 1981-10-27

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