JPS6160092A - Picture memory device - Google Patents

Abstract

PURPOSE:To simplify the constitution of a picture memory circuit by providing at least a means to produce a read address including a displacement of +V to -V lines in the vertical direction, a means to produce a write address of supplementing pixels preceding the read address, and a memory section constitut ed by the L numbers of memory units. CONSTITUTION:Input picture signals are supplied to a noise rejection circuit 10 through a line 100. The noise rejection circuit 10 stores a screen of data, rejects noises between screen data, and supplies the output of a delay circuit 11 and a vector detector 17 through a line 110. The noise rejection circuit also supplies picture signals delayed by a screen to the vector detector 17 through a line 1017. The vector detector 17 uses the 2 types of signals to detect moving vectors, outputting them through a line 1700. Delay in a variable delay circuit 16 is set so that the sum of delay time to frame memory 15 may be just equal to a screen time with the moving vector being zero or a static screen and is incremented or decremented according to delay time indicated by the moving vector.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a memory device for storing image signals.

(Prior art and its problems) Various coding methods for moving image signals are known and have been put into practical use, but among them, one that is considered to be particularly effective is interframe coding for television W/signals. There is encoding. This encodes changes between ZrfM planes, that is, differences between screens, and is extremely effective when there are many stationary parts.

On the other hand, if there are many moving parts, the effectiveness will decrease. For this reason, "motion compensation" is effective for the moving portion Vζ by shifting the prediction signal by the amount of displacement between the screens. That is, as shown in Fig. 2, a motion vector (Vop) is detected from the input video signal, and a predicted signal is generated by increasing or decreasing the delay for one frame time by the amount of displacement indicated by this vector. This is then used to perform predictive encoding.
``When realizing ``motion compensation'' as a device, it is generally not easy to detect displacement between screens, but for example, as shown in Japanese Patent Application No. 55-126125, it is composed of N lines x M pixels. It is detected what displacement is given to the block to minimize the intra-block sum of evaluation function values at each pixel position, such as error power, and the displacement at that time is taken as a motion vector. There is a method called block matching. If you try to do this in real time for a signal with a high sampling frequency, such as a television signal,
Particularly in calculating the evaluation function, a considerable degree of parallel processing is required. If we do not perform approximate calculations (Ni1M
) parallelism is required.

As shown in Figure 3, when the motion compensation range for each block in the screen is set to ±H pixels/frame horizontally and ±V pixels/frame vertically, it corresponds to all displacements within this motion compensation range. In order to find the evaluation function value, for each pixel in the block, (2H+1)X (2v+1)
pixel, -jl) each 7" mouth tlcTH, teha (2H
+M) x (2V+N) m elements) two-dimensional memory is required. However, the point at the upper left corner of the block is the same as the point at the lower right corner (2H + 1 x (2V + 1) (D
1%') 4bThe parts on both sides that need to be memorized are of course not the same.

However, as a simple method to avoid complicated address control, it is also possible to store data in a wide range, so to speak, regardless of the pixel position within the block, as shown in FIG. That is, by storing (2V+N)X (2H+M) pixels, all pixel positions can be handled. However, in order to perform real-time operation, while the evaluation function is being calculated for a certain block, the pixels within the new compensation range required for the next block must be replenished by the end of the processing of the previous block. Sagiha must. Tsum vN×M
(2V+N) in (replenishment area) in Figure 3 within pixel time
M pixels must be replenished. Therefore, if one pixel time is afc, ((2V+N)×Ml/(N×M)
= (2V+N)/N pixels need to be replenished. If V
=N, (2N+N)/N=3, that is, three pixels need to be replenished within one pixel time. However, since the sampling frequency of television signals is often selected to be around 10 MHz, there is generally no time to fill three pixels sequentially within one pixel time. Therefore, three pixels have no choice but to be supplemented in parallel. This can be easily achieved by dividing the memory into three large groups as shown in FIG. 3 and replenishing them in parallel in three memory groups: DO, DI, and Dz. In the example shown in Fig. 3, the time sequence of the supplied pixels cannot be realized unless the pixels in each block are in an order other than that of each other, which is approximately the same as the scanning order in a normal television signal. It's different. In the above example, V- and -N are used, but the same holds true even if v<N. It is obvious that in the case of VAN, three parallel supplements are required.

FIG. 4 shows an example in which the intra-block summation of the evaluation function is calculated by inputting the three parallel data of Do, Dl, and Dz. Here, an example will be shown in which there are J arithmetic circuits ALU including the two-dimensional memory shown in FIG. 3 (U=N×M). If v=N, pixel data DO, Dl are supplied to three memory groups.

Dz can be replenished by sequentially storing data at the same location in each memory group. This address is indicated by W. Reading is somewhat different from storing (=writing).

The comparison/control unit sets the trial motion vector to be compared to, for example, the pixel position of the upper left corner of the block (
2D 7)”res(Zx, Zy) = (0-, 0
) and output it as R. If one ALLJt- is assigned to each pixel position (Zx, Z,), N,X:M ALUs are required. Also, −0≦Zx≦M−1.0≦2. ≦N-1.

Therefore, for ALUK located at pixel positions ZX\0, zy\0, each X, Y
By modifying the addresses of the components with Z, x, and Zy, the evaluation function [(layer) total'fLk
Execute. The intra-block summation of this seasonal fruit is compared for each trial vector, giving the minimum value fc''$:, and the action vector is selected as the motion vector.

The conventional methods described in detail above have various disadvantages in terms of circuit implementation. This will be explained below.

In the above explanation, N;■ was assumed, but in reality, this assumption is a strong constraint on the circuit configuration.

Since the number of parallels is (2L4-N)/N, if V is a multiple (including N) of N, it will be an integer value, but if it is not a multiple, it will not be an integer a value. In other words, the fact that it is not an integer value means that the look-in address when replenishing the two areas DO and D2 is the address 5. for replenishing Dl. It cannot be used as is as a write-in address.

; In this way, in the conventional example, when V is not a multiple of N, reading and filling (replenishment) for each ALU is performed.
There are many problems, such as the fact that the address signal (W) 'i- cannot be made common, and the supplementary pixel data must be input in parallel to the two-dimensional memory of each AL Ul'l.

(Object of the Invention) The present invention provides a two-dimensional memory that stores pixel data within a motion compensation range and a replenishment area that are used in motion vector detection. The two-dimensional memory T
- For the purpose of configuring.

(Structure of the Invention) According to the present invention, a pixel signal is stored, and pixels included in the block specified for each two-dimensional block unit consisting of N ray/×M pixels are 1. An image memory device that outputs (L≦N×M) images in parallel, the device comprising: (a) means for generating a read address including a displacement of at least +V to -■ lines (■ is zero or a positive integer) in the vertical direction; (bl Means for generating a write address for replenishing pixels preceding the read address.

(c) 2x (N+V) line memories, the read address and the write address are supplied, one of the addresses is addressed using the pixel position in the block, and the other address is It consists of a second read address and a second write address generating means that output the second read address as is, and outputs the second exposed address as Z in the 2 x (N+V) line memories.
An image memory device comprising: a memory section comprising L memory units supplied to XV1N line memories and the second write address supplied to the remaining N line memories; .

(Principle of the invention) Iil to replenishment area! ! In i2 data replenishment, all A
An easy way to standardize addressing (w)y for LU is to first set the number of supplementary data to one (that is, the number of parallels = 1). As shown in FIG. 5, this can be realized by providing a plurality of line memories as a total basic unit. That is, (2V+N) lines are used as a memory for motion compensation f@enclosure, and another N lines are used for replenishment. Therefore, while sequentially calculating motion vectors in the horizontal direction using memora in the motion compensation range,
Replenish the pixel data for the line. That is, the time required to detect motion vectors for all blocks on one block scanning line (scanning line divided by N lines) is exactly N line time, which coincides with the perline replenishment time.

That is, replenishment can be performed for 91 pixels per pixel time, and there is no need to perform replenishment in parallel. As a result, if all ALUs are provided with two-dimensional memories as shown in FIG. 5, at least W can be shared.

Next, how reading/writing is performed in each two-dimensional memory using R and W given in common will be explained.

(1) When performing address designation decoration for each pixel position at the time of reading: This will be explained using (5) and ◎ in FIG. 6.

In this example, the fragrance to the two-dimensional memory is all AL
The same is true for U. Therefore, Fig. 6 (2), (
Motion compensation for the block in the mouth @tBA (f in the figure
(abbreviated as c) is a pixel position within a block - for no i! "I" is set in the two-dimensional memory in the same way: rL. Upper left f(hi: (Kx=Kx=o)
Regarding the pixel a at the pixel position, in the sixth diagram, [1Vi
The pixel ZfC at prime position I is shown in Figure 0, respectively. As shown by thick solid lines, the addresses to be read are different. For example, for the trial action vector V (the X and Y components are Vχ and vY, respectively), the address to be read for pixel a is Rx+Vx, Ry+vY for each X, Y component.
, and for pixel Z RX+Z
-Ry + Z y + V y, respectively.

However, 几X・RY indicates the position tl on the two-dimensional memory when predicting between 7 frames of pixel a of the target block (V = , 0), and this is the reference address of each block. be. Since each ALU differs only in (Zx, zX), Rx+vX, RY+vY can be considered to be the X and Y components of the above-mentioned read address.

In this way, for reading, all ALUs use W as is, and for reading, desired pixel data can be read out simply by modifying the address for the pixel position (Zx, Zy) that each ALU should calculate. .

(2) Address modification for each pixel position during writing Address modification can also be performed during writing.

FIG. 7(4) shows a method of writing in and reading out t for pixel position a and pixel position Z for pixel position β.

As for pixel position a, 2x=2d==0, so it is the same as the case (1) above.

For pixel position 2, if the replenishment is performed at positions shifted left and upward by 2x and 2Y, reading will be performed at the address (RX+vx) at pixel position aK.

Ry + V y ) can be used as is. The same applies to other pixel positions.

That is, the reading address at any pixel position within the block is W and Zx for the X and Y components, respectively.

It is expressed as wY-ZY. Wx, WY are each X of W,
Let it be the Y component.

Above, in the explanation of (1) and (2), left → right, top →
The downward direction is the pixel position, and the direction in which the lines increase.

In this way, if a two-dimensional memory is constructed using line memories as basic units, reading and checking (replenishment) for all ALUs can be performed using a common address signal.

(Example) An example will be described with reference to FIG. 1.8.9. First, explanation will be given using FIG. 8.

Noise removal circuit 10 via input image signal F1a1O00
supplied to Noise removal circuit 10 stores one screen, removes noise t existing between one screen, and supplies the output to delay circuit 11 and vector detector 17 via line 1100. Further, an image signal delayed by approximately one screen is supplied from the noise removal circuit 10 to the vector detector 17 via a line 1017.

Vector detector 17 detects a motion vector using these two signals and outputs it via line 1700. This will be explained in detail later.

Corresponding to the loyalty vector supplied via line 1700,
The variable delay circuit 16 delays the image signal from the frame memo +715 and uses it as a predicted signal! 81600 to the subtracter 12 and adder 14. The delay circuit 11 delays the input signal by the time required for the detection and output of the motion vector in the vector detector 17 and supplies it to the subtracter 12 . The subtracter 12 generates a prediction error signal from this delayed signal and the prediction signal supplied from the variable delay circuit 16, and supplies it to the quantizer 13. Quantizer 13 quantizes the prediction error to form line 1300'! i to an adder 14 and an unequal length encoder 18. Adder 14 sums this quantized prediction error and the prediction signal supplied from variable delay circuit 16 to generate a locally decoded signal and supplies it to frame memory 15 .

The delay in the variable delay circuit 16 is set so that when the supplied motion vector is zero, that is, representing a stationary state, the sum of delay times with the frame memory 15 is exactly equal to one screen time, and the delay indicated by the motion vector is It is increased or decreased depending on the delay time.

The unequal length encoder 18 compresses and encodes both the supplied motion vector and the quantized prediction error using unequal length code sounds suitable for each. This output is supplied to a buffer memory 9 that matches the speed when outputting to the transmission line 2000.

Next, the vector detector 17 will be explained with reference to FIG.

In the figure, numerals 171 to 174 are arithmetic circuits including two-dimensional memories, and although it is generally better to use (N x M) circuits, four circuits will be described for simplicity.

The image signal delayed by about one screen time and supplied via #1017' is input to arithmetic circuits (ALU) 171 to 174. The output of the noise removal circuit 10, which is supplied via the other line 110 (l), is similarly input.

2. The address signal (R) used to read out pixel data stored in the two-dimensional memory in the ALU through lines 7001 and 7002, and the two-dimensional memory of pixel data supplied through line 1100. An address signal (W) specifying an address to be added to one is transferred.

The evaluation function 11 f (-1) which is the output from each ALU is all added and supplied to the comparison/control unit 170 as a total sum in block units.

This addition is performed by adders 175, 176, and 177.

The comparison/control unit 170 converts the trial action vector into a two-dimensional memory address for the upper left corner pixel position (Zx, Zy) = (0,0) in the block, and outputs an address signal tR1t- for reading. There are (2H + 1) x (2V + 1) types of trial action vectors, but comparing all of them in real time would require too much equipment, so we tried to reduce the number approximately without lowering the detection accuracy. It is normal to do so.

At this time, of course, depending on the trial action vector used, there may be cases where it is not safe to always operate the two-dimensional memo IJ-.

Then, the sum of the evaluation function values per block for each of the obtained trial action vectors is compared one after another, and the minimum sum is given as Lyt
- line 1 as a motion vector detected in trial motion vector 7;
700.

- Next, a configuration example of the ALU will be explained with reference to FIG. For the address signal H supplied via m7001'r, each ALIJ is
The unique CZx, Zy ) values given to the horizontal (
X) and vertical (Y) components are added by an adder 705,
Qualifications are made. This (Zx, Zy) value is for each AL
The value range O≦Zx≦M-1, 0≦Zy≦N- is determined by the pixel level fft in the block that U corresponds to.
It is 1. The result of this addition is provided via line 7002. :W and switch 704 alternately select read/'4J@include address signal to 2-dimensional memory 70
0 address input. Using FIG. 5, the adder 70 is used to read out the pixel data for strabismus.
5, the signal W supplied via line 7001 is used to write pixel data into the (replenishment area).

Of course, it goes without saying that a particular IALU does not perform a read operation for all of the pixels within the diagonal line. The -fc pixel data supplied via line 1017 is applied to each ALU's pixel location (Zx, Z
Only those corresponding to y) are stored in the memory 702 of each ALU. Therefore can ALU memo! J-702
Pixel data is stored for every N lines and for every MIII pixel. Although it is read out from the memory 702 with a delay of N lines, the output of Jin is read from the two-dimensional memory 70.
It is subtracted from the output of 0 in a subtracter 701. The difference (li
) is subjected to conversion in the form of a ratio, for example, a square operation, to f (p) in the conversion circuit 703 and is output. This f(li
) is the output of the first ALU. The conversion f(・) is common to all ALUs, but usually the readout memo IJ
It is also easy to perform a conversion that includes weighting for a specific pixel position M (for example, near the center of a block) of the 1ζth specific pixel position realized in (ROM).

In addition, in FIG. 9, each pixel position R (
In contrast to the example in which address modification is performed using Zx, Zy)) ζ, FIG. 10 shows a case in which address modification is performed on the replenishment overheating address signal (W). That is, R is connected to the switch circuit 704 as it is to the line 700.
1, while W is supplied via the offset circuit 7
06 gives an offset of the pixel position (Zx, 2 pixels) to each ALU, and the difference created by the subtracter 707 (
Wx Zx.

WY-ZY) is supplied to the switch circuit 704 as a write address signal.

In the embodiment described above, as shown in FIG. 8, motion vector detection was performed at a location completely separated from the predictive coding loop, but the present invention is not limited to this.

Frame memory 5 fed via input image signal line 1500 fed via line 1000' as two signals to be fed to vector detector 17 as shown in FIG. 1L.
It is also possible to use the output signal of

The output signal of this frame memory 5 corresponds to the signal supplied via the line 1017, and the input image signal corresponds to the output of the noise removal circuit 10, respectively.

t7'2: The configuration of the ALU shown in FIG. 9 can be easily applied to the variable delay circuit 16.

Assuming that the motion vectors that are the output of the vector detector 17 supplied via the line 1700 and the time series of the processing in predictive coding are the same as in ordinary television signals, each of the motion vectors X, The Y component (Zx.

Zy) and (b) R supplied via line 7001 spreads an area of N line width in the vertical direction from the top line to the bottom line, which corresponds to when the change is zero in FIGS. 5 and 6. ~V is generated so as to scan along the time series of the television signal and is supplied via the (=-1 gauze 7002'), and is scanned in the same manner as in the case of R and in the (replenishment area) of Fig. 5.6. ) portion, that is, V lie/is generated to indicate the preceding position, and the output of the two-dimensional memo IJ-700 becomes the predicted signal output via m1600' (c-).

If the scanning order of the output motion vectors of the vector detector 17 is rearranged in units of blocks a2.

The motion vector is constant between one block, but in this case, it is easy to configure the same as (c)t described above, except that the order of traversal is different for (portion 1f'l).However, in this case, the delay circuit In step 11, it is necessary to rearrange the image signals in all steps so that the scanning order matches.

Note that the supplementary data to the variable delay circuit 17 is explained in the ninth section.
Line 1100 in the figure should be read as line 1500. subtractor 70
The 1% memo +3-702 and the conversion circuit 703 are unnecessary in the variable delay circuit.

When operating as the variable delay circuit 17, both input and output
Although it differs from the two-dimensional memory used in motion vector detection and the continuous marking of each i pixel, the basic configuration can be said to be almost the same.

(Effects of the present invention) Since the basic unit of the two-dimensional memory is a line, the offset (Z
x, Zy) are manually inputted read address signal R (or deaf address signal) V),
A memory valley modified only by JLI''pf-(n)1-R is obtained, and the configuration is extremely simple. That is, L#r,l common to all ALUs.

This technique that can supply K is obtained by modifying the read address signal for interframe prediction with each trial motion vector, but it is also possible to addition (subtraction if it is a negative number)
It is easier to obtain than K.

A similar effect can be obtained in the generation of the read address signal when the variable delay circuit 16 generates the predicted signal using the detected perturbation vector.

Furthermore, the time series of the signal replenished into the two-dimensional memory, which uses lines as its basic unit, can be processed either by normal television scanning or by converting the time series into N line units for the next scan. Not only can a pair be easily provided, but also when replenishing, it is only necessary to supply one pixel at a time, without the need for parallel supply as in conventional columns.

When the present invention is put to practical use in this way, the effects are very large.

[Brief explanation of drawings]

Figure 1 is a diagram explaining motion vector detection according to the present invention. Figure 2 is a diagram explaining motion compensated interframe predictive coding.
The figure is a diagram explaining the structure of a conventional two-dimensional memory and a method of detecting a motion vector.
．． FIG. 11 is a diagram illustrating an embodiment of the present invention. In the figure, lO is a noise removal circuit, 11 is a delay circuit, 12 is a subtraction circuit, 13 is a quantizer, 14 is an adder, 15 is a frame memory, 16 is a variable delay circuit, 17 is a vector detector, and 18 is an inverter. 19 is a buffer memory. −To〉−Rakuichi 2←14− ) −Hair← 〉→−−
2-+-G-〉-Sito2→Tei 6 Ki (A An (B) (A) (B) Multi 10 Figure

Claims (1)

[Scope of Claims] An image in which an image signal is stored and L (L≦N×M) pixels included in a block specified for each two-dimensional block consisting of N lines×M pixels are output in parallel. A memory device comprising: (a) means for generating a read address including a displacement of at least +V to -V lines in the vertical direction (V being zero or an integer); (b) for replenishing pixels preceding the read address; (c) 2×(N
+V) line memory, the read address and the write address are supplied, one of the addresses is modified using the pixel position within the block, and the other address is output as is. address and a second write address generating means, the second read address is supplied to 2×V+N line memories among the 2×(N+V) line memories, and the remaining N line memories an image memory device comprising: a memory unit configured from L memory units to which the second write address is supplied;