JPS6159693A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable the functional test without employing memory elements for the testing by incorporating a circuit for turning all of the row lines to the non-selective mode to output the data before the writing. CONSTITUTION:A column decoder 14 of NAND structure is incorporated with a circuit for turning all of the row lines to the non-selective mode. When a non-selective signal 13 is turned to the L-level, the output from inverter 15 is turned to the L-level, irrespective or an address 12 and a row line 21 is turned to the L-level through a depression type N-transistor 16 to be non-selective. Hence, the function test of writable read-only semiconductor device for writing the threshold voltage in the direction of OFF can be performed without providing any memory element for testing and the peripheral circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention 1-T8 is concerned with a test circuit for a semiconductor memory device consisting of a read-only semiconductor memory device, particularly a (floating gate trench MOS) transistor. .

[Prior art]

In general, a writable read/write semiconductor memory device [Before writing data, all data is ``01'' or ``1''
' is in a fixed state, and if a function test is performed in this state, it is always in the same state and it is impossible to determine whether it is functioning or not.

Conventionally, such a semiconductor memory device was disclosed in Japanese Patent Application Laid-open No. 59-22
As in Publication No. 99, test column lines (word lines in the above document) were provided, and tests were performed using test memory elements. An example of this is shown in a block diagram in Figure 2. 10~1z, 2Q~field, ke address input,
~3n data input/output terminals, 4.6 is address buffer circuit, 56 row decoder, 7 digit column decoder, 8 is memory element array, 9 digit test memory element array, 10 is row selector, 11 digit output circuit It is. In Figure 2, when reading normal data, address inputs 10 to 1z, 2r
When an address input signal is input after 1 to 2 m, it passes through an address banoff 74.6, and a memory element equal to the number of input/output terminals is selected by a decoder 5.7 and a row selector.
Data is output via the output circuit 11. When performing a functional test in front of someone writing data, use a test terminal, for example, to select a test column line with a column decoder, select a test memory element in the same way as normal, and then Data written in advance in the test memory element is output.

[The problem that the invention attempts to solve]

However, the aforementioned semiconductor memory device requires a special memory element and peripheral circuit for testing, and the semiconductor memory device 1:? This results in an increase in the number of elements, that is, an increase in cost. In particular, in the case of a semiconductor memory device comprising a floating gate trench MOS transistor according to the present invention that can be erased by ultraviolet rays (F:FROM), when the final form is a plastic package,
Functional testing is performed in the state before writing only during shipping inspection, and as described in the above-mentioned document, Japanese Unexamined Patent Publication No. 59-2299, short circuits in the signal lines are unlikely to occur, and the functional testing is mainly performed on the 1lfI line. The present invention is intended to solve these problems, and its purpose is to enable final prototype testing of EP ROMs, especially in non-erasable packaging, without increasing the number of elements. Basically, the purpose is to make it possible to perform a functional test in front of the user even when writing is possible.

[Means for solving problems]

The semiconductor memory device of the present invention is characterized in that it incorporates a circuit that unselects all column lines, which are control gates of memory elements, in a data read state of the programmable read-only semiconductor memory device.

[Effect]

In the writable read/write semiconductor memory device configured as described above, all data is "
01 straddle "1f" is in a fixed state, but EF
In a semiconductor memory device such as a ROM, in which the shy value voltage is written in the off direction, by selecting the column lines to all OFF in the data read state, the memory element will also be in the OFF state for the 5 selected row lines. The device 6 operates as if it were there, outputs the data before writing, and enables a functional test.

〔Example〕

An example is shown in FIG. @1: A signal for deselecting the column line 21 is input to the NAND column decoder, 12-digit address signal, 15 is a signal for deselecting the column line 21, 14-digit column decoder. is NAND
Gate, 15-digit MOS inverter, 16-digit MO when writing
N-channel MO8) transistor for isolating the output T of the S inverter 15 from the program heavy pressure source 20 and below the power supply voltage of the MOS inverter, a gate signal for the 176M0S inverter 16, and a 19-digit column line 21f.

A P-channel MOS transistor 181-t for raising the program voltage is its control signal.

When selecting the column line 21 in the data read state, all the address signals 12 become high level, and the MOS inverter 1
The output terminal of 5 becomes high level, and the N-channel MOS
) Range Meta 161-f is made of depletion type and its gate signal is at high level and MOS inverter 15
The output signal of is transmitted to the column line 21. The gate signal 18 of the P-channel MOS transistor 19 is at a high level during read/write and is in an off state. In this state, the signal 13 for deselecting all column lines is at a high level, and when deselecting, the signal 13 becomes a low level, allowing the column line 21 to be set to a low level, regardless of the address signal.

FIG. 3 shows another embodiment of the invention. The number of column decoders in Figure 2 is equal to the number of column lines, and the NAND gate 14
The address signal of
A pair of complementary signals are connected to each half of the column decoders through the I/F, one of which is at a high level and the other is at a low level.

The address input signal shown in FIG. 3 sets all the column lines to a low level by setting both of the pair of complementary address signals to the same image level. In Fig. 3, 22 is an address input terminal, 25.26 is an address signal, and 24f''t
This is a signal that sets the address signals 25 and 26 to a low level to deselect a column line, and a signal that prohibits address input in the 23-digit standby state. In the normal read state, 1-t23t: is at low level, 24 is at high level, and address signal 25.
26, signals complementary to the address inputs are outputted.

When address signal 24 is set to low level, both address signals 25 and 26 are set to low level, thereby deselecting all column lines.

Next, it will be explained using an example of a data detection circuit of a memory element that by deselecting a column line as mentioned above, both levels 0" and 71' can be extracted as an output signal of a semiconductor memory device. Figure 4 shows an example of this, which includes a power supply terminal for a 27-digit read operation, a 28-digit data write input path, and a P-channel MOS transistor that raises the output terminal 37 to a high level when the 29-digit memory element 36 is in the on state. , 511- is an N-channel MOS transistor that switches between writing and reading, 32 digits control signal, 3 squares is a row selector N-channel MO8) run star, 336 row decoder output line, 35 column line, 38 column line, 40 P-channel MO8 transistors forming a sense amplifier
; KVCN transistor 211MO3) transistor, output terminal of 41. The memory element 36 is a floating gate N-channel MOS transistor, and is a memory element in which floating gate VC electrons are injected by applying a high voltage to the gate and drain terminals to oxidize the critical value and pressure to write data. It is. When the memory element 66 is not being written, normally its threshold voltage is 1 to 2V, and the 1st column line 35 is selected, and when the high level is busy, the memory element 36 is turned on, and when the row line 38 is selected. The output line 53 of the row decoder goes high, and the row selector 54 turns on. I-t52 in read/read state
The switching MO8) transistor 31 is also on, and it is at a low level when reading 29. All the MO3h runnostars are turned on from the E source terminal 27 to the ground, and each impedance has a potential of 37.38, which is normally set to be 37 times lower in this state.

As a result, the output terminal of the sense amplifier becomes high level. Next, when data is being written into the memory element 66, the value voltage of the memory element 66 is normally about ri1av, and even if the column @55 is high 17 bells, the potential of the memory element 36 is turned on and the potential of 57 is The voltage rises to the potential of the power supply terminal 27, and the output of the sense 7 amplifier becomes low level.

Although binary values are stored in this way, when the row line 38 is selected and all lines including the column line 35 become low level as described above, the data is written to the memory element 36. In both cases, a low level is output to the sense amplifier in the same manner as in the above-mentioned state.

Next, FIG. 5 shows an embodiment of the input circuit according to claim 2. There are 42 input terminals, 43f'i enhancement type P-channel Most 7 transistors, 44 N-channel MO51 transistors, and 45 output terminals. When the input terminal 42 is within the power supply voltage range, P
The channel MQS) transistor 43 is in an off state, and the output terminal 451- becomes a low level. When it becomes sufficiently higher than the input terminal 42, the P channel MO9) transistors 46 and N
Both channel MO8 transistors are turned on, and when the input terminal 42 is made high, the output terminal moves to the low level side. In this way, the test function described above can be performed without increasing the number of terminals. Furthermore, although the input voltage higher than the voltage of the f'i lightning source was explained in the embodiment, one can easily imagine a circuit for a lower input voltage. For example, by incorporating a circuit that deselects all column lines, it is possible to perform functional tests without the need for test memory elements even before writing.
Furthermore, the built-in elements are approximately 1.0 elements and 8 degrees, and can be easily realized at low cost without increasing the number of elements.

[Brief explanation of drawings]

Figure i1 is a diagram showing an embodiment of the present invention, in which a 12-digit address signal, an input signal for deselecting a 13-digit column line, and a 14-digit N
AhrD gate, 15 MOS inverter, 161'l
tN channel MOS transistors, 17 gate control signals, 19 P channel MOS transistors, 18 their control signals, 20 write power supply terminals, and 21 column lines. FIG. 2 is a diagram showing an example of a conventional semiconductor memory device.
10~12.20~2g, tit address input terminal,
30 to 3m are data input/output terminals, 4.6Fi address buffer, 5.7 is a decoder, 8 memory element array, 9
memory element array for testing, 10 row selectors, 11
This is an output circuit. FIG. 3 is a diagram showing another embodiment of the present invention. An address buffer includes an input terminal 22, a 23-digit control input terminal, an input terminal for deselecting a 24-digit column line, and 25.
26 is an address signal. FIG. 4 is a data detection circuit diagram explaining the functional test operation, in which 28 is a data write entrance path, 51, 54° 40dN channel #MOSh 5 n') star, 3Q, 39t:t
P channel MO8) transistor, 29.32 is a control signal, an output line of a 35-digit row decoder, a 35-digit column line, and a 36-digit memory element. FIG. 5 is a diagram showing an embodiment of the present invention, and is a circuit from which a signal can be obtained when a high voltage is input. 42 is an input terminal, and 43 P-channel MO8) transistors. There are 44 N-channel MOS transistors and 45 output terminals. The above people are Suwa Seikosha Co., Ltd.

Claims (2)

[Claims] (1) A writable read-only semiconductor memory device, characterized in that the semiconductor memory device has a built-in circuit that sets all column lines, which are control gates of memory elements, to a non-selected state in a data read state of the semiconductor memory device. . (2) The semiconductor memory device according to claim 1, further comprising a built-in circuit that sets all column lines to a non-selected state when the voltage of the input terminal is set to be higher than or lower than the power supply voltage.