JPS6158334A - Automatic gain controlling system - Google Patents

Automatic gain controlling system

Info

Publication number
JPS6158334A
JPS6158334A JP17945784A JP17945784A JPS6158334A JP S6158334 A JPS6158334 A JP S6158334A JP 17945784 A JP17945784 A JP 17945784A JP 17945784 A JP17945784 A JP 17945784A JP S6158334 A JPS6158334 A JP S6158334A
Authority
JP
Japan
Prior art keywords
signal
amplitude
discriminating section
pattern
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17945784A
Other languages
Japanese (ja)
Inventor
Noriaki Kondo
近藤 則昭
Masaki Kobayashi
正樹 小林
Shigeru Ono
茂 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP17945784A priority Critical patent/JPS6158334A/en
Publication of JPS6158334A publication Critical patent/JPS6158334A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/02Details
    • H04B3/04Control of transmission; Equalising

Abstract

PURPOSE:To stabilize an automatic gain controlling system composed of an amplitude discriminating section, pattern discriminating section, AGC amplifier, etc., by bringing the output signal level nearer to a reference value only when an input signal is the same as or similar to a training pattern. CONSTITUTION:An adder circuit 5, inter-code interference quantity discriminating circuit 8, equalizing pulse generating circuit 9, and adder circuit input terminal 6 and output terminal 7 constitute a decision feedback type transversal equalizer. Signals outputted to the output terminal 7 are added to an amplitude discriminating section 10 and pattern discriminating section 15 and the output signal of each section 10 and 15 is supplied to the two input terminals 12 and 13 of a gain control discriminating section 11. The discriminating section 11 discriminates that the output signal of the amplitude discriminating section 10 is effective when the signal of the input terminal 13 is '1' and supplies the gain controlling signal of an AGC amplifier to a terminal 3 from the output terminal of the discriminating section 11. Therefore, only when the signal inputted in an input terminal 1 is the same as or similar to a training pattern, it is discriminated that whether the scale of the amplitude of the signal is larger than a reference value or not and the output signal level is controlled so as to bring the level close to the reference value.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、ディジタル加入者紛伝送装置の自動利得制
御方式に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an automatic gain control system for a digital subscriber traffic transmission device.

(従来の技術) ディジタル加入者線自動等化器において、例えば、電子
通信学会C383168rディジタル加入者線自動等化
系の一検討J1984年1月27日、K示す様に1該自
動等化器の自動利得制御(AGC)及びブリッジタッグ
用非線形等化制御(IIT制御)の手順は、大別して (1)  )レーニングパターン(周期孤立)4p −
/1.0,0,0,0.0.O,Oの繰返し)受信によ
るAGC(便宜上、r AGC−I Jという)、及び
BT制御(便宜上、rBT−IJという) (2)  前記(1)環レディ後、情報(ランダムノ?
ターン)受信によるAGC(便宜上rAGC−2Jとい
う)、及びBT jli制御(便宜上r13T−2Jと
いう)がある。
(Prior art) In the digital subscriber line automatic equalizer, for example, as shown in IEICE C383168R Digital subscriber line automatic equalization system study J, January 27, 1984, K. The procedures of automatic gain control (AGC) and nonlinear equalization control for bridge tags (IIT control) can be roughly divided into (1) ) laning pattern (periodic isolation) 4p -
/1.0,0,0,0.0. AGC (for convenience, referred to as rAGC-IJ) and BT control (for convenience, referred to as rBT-IJ) by receiving (repetition of O, O) (2) After the ring is ready in (1) above, information (random?
BT jli control (r13T-2J for convenience) and BT jli control (r13T-2J for convenience).

八GC−1、AGC−2は共に、自動等化器の出力信号
のピーク値を検出し、その結果をもとに利得を制御する
ものである。
Both GC-1 and AGC-2 detect the peak value of the output signal of the automatic equalizer and control the gain based on the result.

従来方式のAGC−1とAGC−2は、出力信号のピー
クを検出する方法が全く同一手段で行ない、異なってい
る点は利得を更新するときに、例えばAGC−1では出
力信号のピーク値が基準電圧を越える毎に利得を更新す
るか、NIピット受信する間KM、ビット以上基準電圧
値を越えた時利得を耐折する、またAGC−2では同様
KN2ビット受信する間にN2ビット以上基準電圧値を
越えた時利得を更新する。一般に、N+/M+ > N
2/M2 (但しMl<N2とする。)である。これは
運用時には平均時間を長くとり、雑音による誤動作を防
ぐ目的である。
Conventional AGC-1 and AGC-2 use exactly the same method to detect the peak of the output signal.The difference is that when updating the gain, for example, in AGC-1, the peak value of the output signal is The gain is updated every time the reference voltage is exceeded, or the gain is updated when the reference voltage value is exceeded by KM bit or more while receiving NI pits, or the gain is updated when the reference voltage value is exceeded by more than KM bits while receiving NI pits.Also, in AGC-2, the gain is updated when the reference voltage value is exceeded by more than N2 bits while receiving KN2 bits. When the voltage value is exceeded, the gain is updated. Generally, N+/M+ > N
2/M2 (Ml<N2). The purpose of this is to increase the average time during operation and prevent malfunctions due to noise.

また、BT−1,BT−2は符号の識別を行う時間にお
ける符号量干渉が小さくなるように大きさの異る等化ノ
4ルスを加えて非線形等化を行なう。13T−1゜BT
−2において、BT−2では入力される信号がランダム
/4’ターンでアルので、トレーニンf /4’ p 
−7と同様のパターンが受信されたときに符号量干渉の
大きさを検出し、それをもとに等化係数の更新を行う。
Furthermore, BT-1 and BT-2 perform nonlinear equalization by adding equalization pulses of different magnitudes so as to reduce code amount interference at the time of code identification. 13T-1゜BT
-2, in BT-2, the input signal is random/4' turn, so the training f/4' p
When a pattern similar to -7 is received, the magnitude of code amount interference is detected, and the equalization coefficient is updated based on it.

BT−1と異る点はう/ダムパターンノ中かラトレーニ
ングノぜターン判定部のノやターン判定部する手段であ
る。
The difference from the BT-1 is the means for determining whether a turn is determined during a crawl/dumb pattern or during a late training nozzle.

前記(1)項から(2)項の動作に移った時、前述の如
<、BT−1において、符号の識別時点において符号量
干渉が零になっているので、BT−2に移ったとき符号
識別時点では、符号量干渉が零で識別点の振幅も基準値
に収まっている。しかし、符号識別時点以外の点では、
杓号間干渉の大きさを監視していないので、ランダムパ
ターンを受信した時に、等止器の出力信号の振幅が符号
量干渉のだめに符号識別点の基準値よりも大きくなるこ
とがある。この様子を示す等化層出力アイパターンを第
2図に示す。これは、 信号ピットレート 320kbit/s主線路長  2
500 m ブリノソタノプ長  20OFFI  1本600FM
 2本 線種  0.51jφCCPケーブル であり、前記(1)項の動作が終了し、利得及び非線形
等止器のタッグ係数を固定して、ランダムパターンを入
力した時の出力アイノーターンである。
When moving from the operation described in (1) to (2) above, as described above, in BT-1, the code amount interference is zero at the time of code identification, so when moving to BT-2. At the time of code identification, the code amount interference is zero and the amplitude of the identification point is within the reference value. However, at points other than the point of code identification,
Since the magnitude of inter-signal interference is not monitored, when a random pattern is received, the amplitude of the output signal of the equalizer may become larger than the reference value of the code identification point due to code amount interference. An equalization layer output eye pattern showing this situation is shown in FIG. This is: Signal pit rate 320kbit/s Main line length 2
500 m Blinosotanope length 20OFFI 1 piece 600FM
This is a two-wire type 0.51jφ CCP cable, and this is the output eye-turn when a random pattern is input after the operation in item (1) is completed, the gain and the tag coefficient of the nonlinear equalizer are fixed, and a random pattern is input.

(発明が解決しようとする問題点) 第2図に示す様に等止器の出力信号の振幅が基準値を越
えることになるので、AGC−2では利得を更新するこ
とKなる。
(Problems to be Solved by the Invention) As shown in FIG. 2, since the amplitude of the output signal of the equalizer exceeds the reference value, it is necessary to update the gain in AGC-2.

13T−2では利得制御増幅器出力信号に対し、符シ3
識別点において符号量干渉が零となるよう係数の掛った
等化、pルスが加えられているので、増幅器出力信号と
等化・やルスの大きさの割合が前記理由で変ってしまう
。よって、符号量干渉が符号識別点において零でなくな
るので、非線形等化係数の更新が必要となる。
In 13T-2, the code 3 is applied to the gain control amplifier output signal.
Since equalization multiplied by a coefficient and p-rus are added so that the code amount interference becomes zero at the discrimination point, the ratio of the magnitude of the amplifier output signal and the equalization/p-rus changes for the above-mentioned reason. Therefore, since the code amount interference is no longer zero at the code identification point, it is necessary to update the nonlinear equalization coefficient.

上述の様に1第(1)項の動作から@(2)項の動作に
移ったとき伝送路の条件によっては適応動作を必要とす
る欠点を有した。
As mentioned above, when moving from the operation described in item 1 (1) to the operation described in item (2), there is a drawback that an adaptive operation is required depending on the conditions of the transmission path.

(問題点を解決するための手段) 本発明は、周期孤立波をトレーニング/lターンとして
用いるディジタル自動等化器の自動利得制御方式に関す
るものである。可変利得制御信号によシ制御される可変
利得増幅器と、等化出力信号より孤立パターンを検出す
るノ(ターン判定部と、前記検出時に孤立パターンの振
幅の基へ(値からずれを判定して前記利得制御信号とす
る振幅判定部をそなえる。
(Means for Solving the Problems) The present invention relates to an automatic gain control method for a digital automatic equalizer that uses a periodic solitary wave as a training/l turn. a variable gain amplifier controlled by a variable gain control signal; a turn determination unit that detects an isolated pattern from an equalized output signal; An amplitude determining section is provided for determining the gain control signal.

(作用) 可変利得増幅部は、等化器系のレベルを調整するための
もので、入力信号を可変利得制御信号により利得制御し
て等止器に出力する。出力信号パターン判定部は受信ラ
ンダムパターンの中からトレーニングノンターン(00
000001のくり返し)及ヒトレーニングパターンと
同様のノやターン(例tばooo±1や0000±1・
・・・・・・・ooooooo±1)を検出する。振幅
判定部は等化器出力に現われた出力信号の振幅が基準値
より大きいか小さいかを判定し、その判定により前記可
変利得増幅部に可変利得制御信号信号を送出して制御す
る。この際、・ヤターン判定部カトレーニングノやター
ン又ハトレー二ング・ぐター/と同様の74ターンを検
出したことにより、振幅判定部が可変利得制御信号を送
出する。この上うに、トレーニングノぐターフ又は)レ
ーニング・ぞターンと同様のパターンを検出した時のそ
の”±1′の振幅のみを利得更新のための情報として扱
う事により、手順(1)から手順(2)に移った時に発
生する不要な更新動作をなくし、系の安定を図る。
(Function) The variable gain amplification section is for adjusting the level of the equalizer system, and controls the gain of the input signal using a variable gain control signal and outputs it to the equalizer. The output signal pattern determination section selects a training non-turn (00
000001 repetitions) and turns similar to the training pattern (e.g. tbaooo±1 and 0000±1・
......oooooooo±1) is detected. The amplitude determination section determines whether the amplitude of the output signal appearing at the equalizer output is larger or smaller than a reference value, and based on the determination, sends a variable gain control signal to the variable gain amplification section for control. At this time, the amplitude determination section sends out a variable gain control signal by detecting 74 turns similar to the ``yaturn determination section'', ``cut training'' and ``turn'', or ``pigeon training'' and ``gutter''. Furthermore, by treating only the amplitude of "±1'" when a pattern similar to a training turn or training turn is detected as information for updating the gain, step (1) to step ( Eliminate unnecessary update operations that occur when moving to 2) to stabilize the system.

(実施例) 第1図は、本発明の実施例を示す構成図である。(Example) FIG. 1 is a configuration diagram showing an embodiment of the present invention.

受信信号は入力端子Iを通じて自動利得制却増幅器(A
GC増幅器)4に加えられる。AGC増幅器4は利得制
御端子3に加えられる利得制御信号をもとに利得を可変
増幅し、出力信号を端子2へ出力する。該AGC増幅器
4の出力信号は加算回路5の一つの入力端子へ加えられ
る。
The received signal is passed through the input terminal I to an automatic gain control amplifier (A
GC amplifier) 4. The AGC amplifier 4 variably amplifies the gain based on the gain control signal applied to the gain control terminal 3 and outputs an output signal to the terminal 2. The output signal of the AGC amplifier 4 is applied to one input terminal of an adder circuit 5.

加算回路5、符号量干渉量判定回路8、等化・ぐルス発
生回路9、加算回路入力端子6及び出力端子7は従来か
らよく知られている判定帰還形のトランスパーサル等化
器を構成している。
The addition circuit 5, the code amount interference determination circuit 8, the equalization/Grus generation circuit 9, the addition circuit input terminal 6, and the output terminal 7 constitute a conventionally well-known decision feedback type transparsal equalizer. are doing.

一方、等化器の前記出力端子7に現われた等止器出力信
号は、振幅判定部IO及び・!ターン判定部15に加え
られ、それぞれの出力信号は利得制御判定部11の二つ
の入力端子12 、7.7に加えられる。利得制御判定
部1ノの出力端子14より出力される信号はAGC増幅
器4の利得制御端子3へ加えられる。
On the other hand, the equalizer output signal appearing at the output terminal 7 of the equalizer is transmitted to the amplitude determining section IO and...! The respective output signals are applied to the two input terminals 12 and 7.7 of the gain control determining section 11. A signal output from the output terminal 14 of the gain control determination section 1 is applied to the gain control terminal 3 of the AGC amplifier 4.

振幅判定部10は、等化器の出力端子7に現われた出力
信号の振幅が基準値(正負の両方)よシ大きいか、小さ
いかにより異なった制御信号を発するものである。また
、ツクターン判定部I5は出力端子7に現われるう/ダ
ムノンターンの中からトレーニングノやターン(000
00001のぐシ返し;周期孤立)Pターン)と同−又
は同様なノぐターン(例えば、”0”が4ビット以上続
いた後に1″があるような・セターン)が受信されたこ
とを判定するものであシ、同−又は同様なパターン(孤
立波)が受信された時、端子ノ3には”1”、それ以外
の時に“O″を出力する。
The amplitude determining section 10 generates different control signals depending on whether the amplitude of the output signal appearing at the output terminal 7 of the equalizer is larger or smaller than a reference value (both positive and negative). In addition, the turn determination unit I5 outputs a training turn or a turn (000
Determines that a nog turn that is the same as or similar to a 00001 nogashi return (periodic isolation) P turn (for example, a set turn in which there is a 1" after 4 or more bits of "0") is received. When the same or similar pattern (solitary wave) is received, "1" is output to terminal No. 3, and "O" is output at other times.

制御判定部IIは、端子13の信号がl”になったとき
振幅判定部’10の出方信号を有効とし、i1+lI 
l111判定部11(7)出力端子14 ヨり AGC
増幅器4の利得制御信号として端子3へ加えるダート回
路である。よって振幅判定部I Q 、 /4’ターン
判定部/ 、i、出力端子I4、AGC増幅器4で構成
される自動利得制御系は、入力端子IK人カされた信号
がトレーニングパター7と同−又は同様のときにのみ、
その信号の振幅の大きさが基準値よシ大きいか小さいか
を判定しそれをもとに1出力信号レベルが基準値に近づ
くよう制御する。
The control determination unit II validates the output signal of the amplitude determination unit '10 when the signal at the terminal 13 becomes l'', and i1+lI.
l111 judgment unit 11 (7) output terminal 14 Yori AGC
This is a dart circuit that is applied to terminal 3 as a gain control signal for amplifier 4. Therefore, the automatic gain control system composed of the amplitude determining section IQ, /4'turn determining section/, i, the output terminal I4, and the AGC amplifier 4 is configured such that the signal applied to the input terminal IK is the same as the training pattern 7, or Only when similar
It is determined whether the magnitude of the amplitude of the signal is larger or smaller than the reference value, and based on this, the level of one output signal is controlled so as to approach the reference value.

従っテ、トレー二/グパターンカラランダムノぞターフ
に変っても、利得制御に使用する情報自体が同一である
ので、新たな利得の更新やそれKともなう非線形等化部
の等化Aルスの大きさの更新がない。
Therefore, even if the training pattern changes from random color to turf, the information used for gain control is the same, so the new gain update and the equalization A pulse of the nonlinear equalization section There is no size update.

(発明の効果) 以上説明したように、トレーニングノやターフからラン
ダムパターンに変ったときに生じる利得の再更新や、そ
れにともなう非線形等化器のタッグ係数の更新による等
化性能劣化がなく、系の安定化を図ることができるので
、トレーニング・ぞターンを使用する本来の目的を達す
ることになる。
(Effects of the Invention) As explained above, there is no deterioration in equalization performance due to the re-updating of the gain that occurs when changing from a training pattern or turf to a random pattern, and the associated updating of the tag coefficient of the nonlinear equalizer, and the system Since it is possible to stabilize the situation, the original purpose of using the training turn can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の回路口、第2図は出力アイ
ノやターンを示す図である。 1・入力端子、4・・・自動利得制御系増幅2J17・
・・出力端子、IO・・・振幅判定部、I5・・りぐタ
ーン判定部。 第1図 第2図 −助1 手続補正書(鮫) 1 事件の表示 昭和59年 特 許 願第179457号2、発明の名
称 自動利得制御方式 3 補正をする者 事件との関係       特 許 出 願 人任 所
(〒105)  東京都港区虎ノ門1丁目7番12号住
 所(〒105)  東京都港区虎ノ門1丁目7m12
号5補正の対象 明細書中「発明の詳細な説明」の4t
146、補正の内容 明細書第3頁第1行目に「る、ま
た」とあるのを「る。また」と補正する。
FIG. 1 is a diagram showing a circuit port of an embodiment of the present invention, and FIG. 2 is a diagram showing an output eye and a turn. 1. Input terminal, 4. Automatic gain control system amplification 2J17.
...Output terminal, IO...Amplitude judgment section, I5...Rig turn judgment section. Figure 1 Figure 2 - Support 1 Procedural amendment (Shark) 1 Indication of the case 1982 Patent Application No. 179457 2 Name of the invention Automatic gain control system 3 Relationship with the person making the amendment Patent application Address (〒105) 1-7-12 Toranomon, Minato-ku, Tokyo Address (〒105) 1-7m2, Toranomon, Minato-ku, Tokyo
Subject of amendment No. 5: 4t of “Detailed Description of the Invention” in the specification
146. Contents of the amendment In the first line of page 3 of the specification, the phrase "Ru, Mata" is amended to read "Ru. Mata."

Claims (1)

【特許請求の範囲】[Claims] 周期孤立波をトレーニングパターンとして用いるディジ
タル自動等化器の自動利得制御方式において、可変利得
増幅器と振幅判定部とパターン判定部とをそなえ、前記
パターン判定部によって等化出力信号より孤立パターン
を検出し、かつ前記検出時における前記振幅判定部が判
定した孤立パターンの振幅の基準値からのずれの判定値
を前記可変利得増幅器の利得制御信号とすることを特徴
とした自動利得制御方式。
An automatic gain control method for a digital automatic equalizer using a periodic solitary wave as a training pattern includes a variable gain amplifier, an amplitude determination section, and a pattern determination section, and the pattern determination section detects an isolated pattern from an equalized output signal. and a determination value of the deviation of the amplitude of the isolated pattern from a reference value determined by the amplitude determining section at the time of the detection as a gain control signal of the variable gain amplifier.
JP17945784A 1984-08-30 1984-08-30 Automatic gain controlling system Pending JPS6158334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17945784A JPS6158334A (en) 1984-08-30 1984-08-30 Automatic gain controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17945784A JPS6158334A (en) 1984-08-30 1984-08-30 Automatic gain controlling system

Publications (1)

Publication Number Publication Date
JPS6158334A true JPS6158334A (en) 1986-03-25

Family

ID=16066185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17945784A Pending JPS6158334A (en) 1984-08-30 1984-08-30 Automatic gain controlling system

Country Status (1)

Country Link
JP (1) JPS6158334A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000011803A1 (en) * 1998-08-21 2000-03-02 Fujitsu Limited Data transmitter, method for automatically adjusting level, and method for controlling pull-in
WO2008105070A1 (en) * 2007-02-27 2008-09-04 Fujitsu Limited Adaptive equalization circuit
US7477878B2 (en) 1997-06-19 2009-01-13 Mitsubishi Denki Kabushiki Kaisha Data transmission system, data transmitter and data receiver used in the data transmission system
JP2012504901A (en) * 2008-10-02 2012-02-23 アルテラ コーポレイション Automatic calibration in high-speed serial interface receiver circuits.

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7477878B2 (en) 1997-06-19 2009-01-13 Mitsubishi Denki Kabushiki Kaisha Data transmission system, data transmitter and data receiver used in the data transmission system
US7764930B2 (en) 1997-06-19 2010-07-27 Mitsubishi Denki Kabushiki Kaisha Data transmission system, data transmitter and data receiver used in the data transmission system
WO2000011803A1 (en) * 1998-08-21 2000-03-02 Fujitsu Limited Data transmitter, method for automatically adjusting level, and method for controlling pull-in
WO2008105070A1 (en) * 2007-02-27 2008-09-04 Fujitsu Limited Adaptive equalization circuit
JPWO2008105070A1 (en) * 2007-02-27 2010-06-03 富士通株式会社 Adaptive equalization circuit
JP4859977B2 (en) * 2007-02-27 2012-01-25 富士通株式会社 Adaptive equalization circuit
US8270462B2 (en) 2007-02-27 2012-09-18 Fujitsu Limited Adaptive equalizer circuit
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