JPS6158327A - High-speed dpcm encoder - Google Patents

Abstract

PURPOSE:To obtain a quickly operating DPCM encoder, by providing a quantizator, delay element, multiplier, and 3-input and 2-output digital-digital converter. CONSTITUTION:The DPCM signal of the output of a quantizator 3 is inputted by inversion in a 3-input and 2-output DD converter 7 after it is multiplied by a forecasting coefficient of 1/2 by a multiplier 9. Moreover, the value of 1-sampling period before which is the output of an FF 6 is inputted by inversion in the converter 7 after it is multiplied by the forecasting coefficient of 1/2 by another multiplier 10. Two output signals are obtained from the two inputs of the converter 7 and a PCM signal and sent to an adder 8. The added result of the adder 8 is supplied to the quantizator 3 after delaying the result through an FF 2 and the DPCM signal is outputted from the quantizator 3. Since the operating speed of this encoder depends upon the FF 6, quantizator 3, multiplier 10, and converter 7, high-speed processing can be realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a DI)CM used in an image band compression device, etc.
The present invention relates to an encoder, and relates to a high-speed DPCM encoder that can increase operating speed.

r) When band compression is performed using a PCM encoder, it is desirable to be able to increase the operating speed.

[Conventional technology]

FIG. 3 is a block diagram of a conventional DPCM encoder.

In the figure, 1 is a subtracter, 2.6 is a delay element I"F, 3
is a quantizer, 4 is an adder, and 5 is a multiplier for multiplying the prediction coefficient by 1/2.

To explain the operation in Fig. 3, the difference between the input PCM signal and the predicted value is subtracted from 2::l to °C31
The signal is delayed by the quantizer 3, adopted by the quantizer 3, and outputted as a DPCM signal.

On the other hand, this output is also input to the adder 4, and the multiplier 5 multiplies the output of the adder 4 by 1/2 of the prediction coefficient, and the FF 6 adds it to the predicted value from one sampling period before the delay. , this output is multiplied by a prediction coefficient 1/'2 in a multiplier 5 to obtain a predicted value.

In this way, the DPCM encoder of FIG. 3 outputs a quantized DPCM signal.

[Problem that the invention seeks to solve]

However, the operating speed of the DPCMfff signal generator is
FF2. Quantizer 3. It is determined by a loop of adder 49, multiplier 5°, and subtracter 1, and there is a problem that the operation speed is slow.

[Failure to solve the problem]

The above problem is that the output side includes a quantizer that generates an encoded DPCM signal, a first adder, a first multiplier, and a first
a delay element, and the first multiplier multiplies the output of the first adder by a prediction coefficient, the output is delayed by the first delay element, and the first adder multiplies the output by a prediction coefficient. A predicted value detection calculation loop that receives an input and detects a predicted value; a first input is a PCM signal; a second input is a signal obtained by multiplying the output of the quantizer by a prediction coefficient by a second multiplier; A signal obtained by multiplying the signal delayed by the first delay element by the prediction coefficient by the third multiplier is input to the input of 3, and 2 outputs are obtained.
These two inputs are connected to the output of the two-output digital-to-digital converter.
A second adder that adds the outputs is connected, a second delay element that delays this output is connected to the output of the adder, and this output is connected to the input side of the quantizer. Invention high speed D
Solved by PCM encoder.

[Effect]

According to the invention, the operating speed is determined by the second delay element.

It is determined by a quantizer, a second multiplier, a 3-input 2-output digital-to-digital converter, and a full adder, and compared to the conventional case,
A 3-input, 2-output digital-to-digital converter (hereinafter referred to as a 3-input, 2-output D/D converter) has a faster operating speed than a subtracter, so the operating speed can be increased.

〔Example〕

FIG. 1 is a block diagram of the embodiment of the present invention, and FIG. 2 is a diagram of the 3-input 2-output D/D converter, full adder, and FF of the embodiment of the present invention.
FIG.

In the figure, 7 is a 3-input 2-output D/D converter, 8 is an adder, and 9.
10 is a multiplier that multiplies 1/2 of the prediction coefficient, 7-1 to 7
-8 is a full adder with 2 inputs and 1 output.
The 3-input 2-output D/D converter 7 shown in the figure is made up of +14,
8-1 to 8-8 are full adders each having 2 inputs and 1 output, which constitute the adder 8 in FIG. 1, and 2-1 to 2
-9 is FF, which constitutes FF2 in FIG. 1, and the same reference numerals indicate the same functions throughout the figures.

To explain the difference between the case of Fig. 1 and the case of Fig. 3,
The DPCM of the output of the quantizer 3 (No. 3 is multiplied by the prediction coefficient 1/2 in the multiplier 9, is inverted and input to the 3-input 2-output D/D converter 7, and is the output of the FF 6) The value before the sampling period is multiplied by the prediction coefficient 1/2 in the multiplier 10, and
A PC that is inverted and input to the input 2 output digital-to-digital converter 7 and input to the 3 input 2 output D/D converter 7
The difference with No. M13 is calculated and converted into two outputs, and these outputs are added in an adder 8 and input to the ``ζ'' child quantum 3 via F F 2.

In this case, the PCM signal is 8 bits 87 to Δ0, and the multipliers 9 and 10 multiply by 1/2, so that the 8 bits of the output of the quantizer 3) become 7 bits. 86
～BO, C6～CO, 3 input 2 output D/D converter 7
As shown in FIG. 2, the connection diagram between the adder 8 and the FF 2 shows that the signals AO to A7 are input to the carrier nodes of the 2-input and 1-output full adders 7-1 to 7-8. B6~ for 2 inputs
[30°C6 to CO signals are inverted) (However, the MSB full adder 7-8 receives the [36, C6 signal] output) Full adders 8-1 to 8- 8, (However, LSB
One input of the full adder 8-1 is grounded, and an H level is added to the carry input) The carry output is input to the full adders 8-2 to 8-9, and the full adder 8-1 is input to the full adder 8-1. 1-8-8
The carry output of is input to full adders 8-2 to 8-9, and the output is input to F I'' 2-1 to 2-9, delayed, and connected to be input to quantization J:!3. Explanation calculations are performed.

That is, multiplier 9. Since the sum of the outputs of lO has the same predicted value as the output of multiplier 5 in FIG. 3, the operation of subtractor l in FIG. This is performed by an S unit 7 and an adder 8.

In this way, the Cleave-Calpas that determines the operating speed is FFz, m quantifier 32 multiplier 9.3 input 2 output D
/D converter7. Adder 8 becomes adder 8, and when compared with the case of FIG. 3, adder 8 and adder 4 have almost the same operating speed.
Since the three-horn, two-output D/D converter 7 has a faster operating speed than the subtracter 1°, the operating speed can be increased.

〔Effect of the invention〕

As explained in detail above, according to the present invention, a high-speed DPCM encoder with high operating speed can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a diagram showing the connection of the 3-input 2-output D/D converter, full adder, and FF shown in Fig. 1, and Fig. 3 is a conventional DPCM. FIG. 2 is a block diagram of an encoder. In the figure, 1 is a subtracter, and 2.2-1 to 2-9.6 are FFs. 3 is a quantifier, 4.8 is an adder, 5.4), 10 is a multiplier, 7 is a 3-input 2-output digital-to-digital converter, a-t~
8-9.7-1 to 7-8 indicate full adders.

Claims (1)

[Claims] a quantizer that generates a quantized DPCM signal on the output side;
includes a first adder, a first multiplier, and a first delay element, and the first multiplier multiplies the output of the first adder by a prediction coefficient, and the output is multiplied by the first delay element. A predicted value detection calculation loop that detects a predicted value by delaying it with a delay element and inputting it to the first adder; a PCM signal is input to the first input; A signal obtained by multiplying the predicted value by the prediction coefficient by the second multiplier is input to the third input, and a signal obtained by multiplying the signal obtained by multiplying the predicted value by the first delay element by the prediction coefficient by the third multiplier is input to the third input, A second adder that adds these two outputs is connected to the output of a three-input, two-output digital-to-digital converter that has two outputs, and a second delay element that delays this output is connected to this output. , this output is connected to the input side of the quantizer.
encoder.