JPS6158323A - Testing method of data converter - Google Patents

Testing method of data converter

Info

Publication number
JPS6158323A
JPS6158323A JP18096584A JP18096584A JPS6158323A JP S6158323 A JPS6158323 A JP S6158323A JP 18096584 A JP18096584 A JP 18096584A JP 18096584 A JP18096584 A JP 18096584A JP S6158323 A JPS6158323 A JP S6158323A
Authority
JP
Japan
Prior art keywords
digital
converter
dac
signal
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18096584A
Other languages
Japanese (ja)
Inventor
Shigeru Kawada
川田 茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18096584A priority Critical patent/JPS6158323A/en
Publication of JPS6158323A publication Critical patent/JPS6158323A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To highly accurately measure the characteristics of data converters, by adding a digital input signal to a DA converter and sending the output of the DA converter to an AD converter, and then, comparing the digital output signal of the AD converter with the digital input signal. CONSTITUTION:Characteristic tests are performed on the linearity, monotonous increase, offset, mis-code, etc., of an AD converter (ACD) 2 and DA converter (DAC) 3, by comparing a digital input voltage signal impressed upon the DAC 3 from a digital data generator 8 with a digital output voltage signal outputted from the DAC 2 and detected by a digital detector 9. Then the transmission loss, frequency characteristic, transmission loss level characteristic, signal-to- overall distortion power ratio characteristic, etc., of the ADC 2 and DAC 3 are found by the calculation of the digital signal, by controlling the digital generator 8 with a computer which is not shown in the figure, generating a digital AC and impressing the digital AC upon the DAC 3, digital-data detecting 9 the digital AC output voltage signal of the ACD 2, and then, digital-processing the output voltage signal.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、アナログ・ディジタル変換器およびディジタ
ル・アナログ変換器をともに構成要素として含んでいる
機器内の、前記変換器の特性を試験する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a method for testing the characteristics of an analog-to-digital converter and a digital-to-analog converter in a device that includes both the converter as a component. Regarding.

〔従来の技術〕[Conventional technology]

最近のディジタル機器では、例えば音声PCM方式のC
0DECのようにアナログ・ディジタル変換器(以下A
DCという)とディジタル・アナログ変換器(以下DA
Cという)とがともに含まれている場合が多い。この場
合、ADC,DACは直線的な変換特性でなく、非線形
性になっていることが多い。C0DECの場合では、内
蔵されているADCおよびDACの入出力特性は、大振
幅で粗く、小振幅では相対的に細かく量子化されている
In recent digital equipment, for example, audio PCM system C
Analog-to-digital converter (hereinafter referred to as A) like 0DEC
DC) and digital-to-analog converter (hereinafter referred to as DA)
C) are often included together. In this case, the ADC and DAC often have non-linear conversion characteristics rather than linear conversion characteristics. In the case of the CODEC, the input/output characteristics of the built-in ADC and DAC are coarse at large amplitudes and relatively finely quantized at small amplitudes.

C0DECでは、ADCの出力ディジタル信号、DAC
の入力ディジタル信号は符号ピット(1ピツト)とデー
タビット(7ビツト〕の8ビツトで(1り成される。し
かし、上記のように、  ADC,DACの入出力特性
は非線形となっており、細かく量子化されている部分は
、線形の入出力特性のADCまたはDACに換算すると
13ピツトのデータビットに該当するものになる。
In C0DEC, the output digital signal of ADC, DAC
The input digital signal of is made up of 8 bits: code pit (1 pit) and data bits (7 bits).However, as mentioned above, the input/output characteristics of ADC and DAC are nonlinear. The finely quantized portion corresponds to 13 data bits when converted to an ADC or DAC with linear input/output characteristics.

従来、ADC,DACをともに含む機器の内蔵するAD
CまたはDACを試験する場合にも、個々のADC、D
ACについて、その入出力特性を測定していた。すなわ
ちADCの場合には、入力側にアナログ電圧発生器から
の出力を導き、出力側のディシル値を検出し、入力部電
圧を変化して出力特性を得ていた。DACの場合も同様
に個別的に行なう。
Traditionally, AD built into equipment that includes both ADC and DAC
Also when testing C or DAC, the individual ADC, D
The input/output characteristics of AC were measured. That is, in the case of an ADC, the output from an analog voltage generator is led to the input side, the decile value on the output side is detected, and the input voltage is changed to obtain the output characteristics. In the case of DAC, this is done individually as well.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、上記のような、非線形のA D C、DACの
低レベル特性を試験することは、低レベルにおいて精度
の非常に高い測定器ならびに測定技術が要求され極めて
困難である。特に、アナログ電圧発生装陥、発振器、電
圧計等のアナログ測定器において、稍度要Zが厳しい。
However, testing the low-level characteristics of nonlinear ADCs and DACs as described above requires extremely high-precision measuring instruments and measurement techniques at low levels, and is extremely difficult. Particularly, in analog measuring instruments such as analog voltage generators, oscillators, and voltmeters, the consistency requirement Z is severe.

またADC。Also ADC.

DACを内蔵状態で測定するため、アナログ信号線を測
定器まで延長させる必要があシ、ノイズが乗)易い欠点
があった。
Since the measurement is carried out with the DAC built-in, it is necessary to extend the analog signal line to the measuring instrument, which has the disadvantage of being susceptible to noise.

本発明の目的は、上記の欠点全除去し、アナログ信号6
111定を排除し、ディジタル信号の(ljl定のみで
ADC,DACLv特性を試験し、高精度でかつ測定が
容易に行ない得る方法全提供することにある。
The purpose of the present invention is to eliminate all the above-mentioned drawbacks and to
The object of the present invention is to provide an entire method that eliminates the 111 constant and tests the ADC and DACLv characteristics using only the (ljl constant) of a digital signal, allowing high accuracy and easy measurement.

〔問題点を解決するための手段〕[Means for solving problems]

本発明による試験方法は、機器内に含まれるディジタル
・アナログ変換器、アナログ・ディジタル変換器を試験
する几めに、前記ディジタル・アナログ変換器に前記ア
ナログ・ディジタル変換器を縦続接続し、前記ディジタ
ル・アナログ変換器にディジタル人力信号を入力し、前
記アナログ・ディジタル変換器のディジタル出力信号音
とりだし、上記ディジタル入力信号とディジタル出力信
号との関係から前記ディジタル・アナログ変換器とアナ
ログ・ディジタル変換器との特性全試験するものである
In the test method according to the present invention, in order to test a digital-to-analog converter and an analog-to-digital converter included in a device, the analog-to-digital converter is cascade-connected to the digital-to-analog converter, and the・Input a digital human signal to the analog converter, extract the digital output signal sound of the analog-to-digital converter, and determine whether the digital-to-analog converter and the analog-to-digital converter are connected based on the relationship between the digital input signal and the digital output signal. All characteristics of the test are tested.

〔f′11:  柑〕 本試験方法では、ディジタル・アナログ変換器の出力で
あるアナログ信号は直ちにディジタル・アナログ変換器
に人力させ、その間のアナログ信号の配線長を極めて短
かく出来るので、ノイズが乗ることをさけることができ
る0またアナログ関係の発振器・電圧計などはすべて不
要となり、ディジタル測定のみによってデータ変換器の
特性を試験することができる。
[f'11: Kan] In this test method, the analog signal that is the output of the digital-to-analog converter is immediately transferred manually to the digital-to-analog converter, and the wiring length for the analog signal in between can be extremely short, so noise is reduced. In addition, all analog-related oscillators, voltmeters, etc. are no longer required, and the characteristics of the data converter can be tested using only digital measurements.

〔実 施 例〕〔Example〕

以下、本発明の一実施例につき、図面にもとすいて説明
する。第1図は試験方法を説明するための回路ブロック
図である。機器1内に含まれるADC2,DAC!l全
、図示のようにDAC5のアナログ出力端子7を極力短
かい結線10でADC2のアナログ入力端子4につなぎ
、縦続接続する。
Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. FIG. 1 is a circuit block diagram for explaining the test method. ADC2 and DAC included in device 1! 1. As shown in the figure, the analog output terminal 7 of the DAC 5 is connected to the analog input terminal 4 of the ADC 2 with the shortest possible connection 10, making a cascade connection.

(−して、DAC3のディジタル入力端子6からディジ
タルデータ発生器8のディジタル信号電圧を印加し、A
DC2のディジタル出力端子5の出力をデイジタルデー
タ検出器9に人力する。
(-, apply the digital signal voltage of the digital data generator 8 from the digital input terminal 6 of the DAC 3, and
The output of the digital output terminal 5 of the DC 2 is inputted to the digital data detector 9.

上記のような試験回路において、先ずADC2+DAC
5の直流特性の試験方法を説明する◎ディジタルデータ
発生器8から、DAC3に印加するディジタル人力′屯
圧倍号とADC2から出力されディジタルデータ検ll
f:I器9で検出したディジタル出力電圧信号とを比較
することで、ADC2およびDAC3の直線性・単調増
加性・オフセットおよびミスコード等につき特性試験を
行なうことができる。
In the above test circuit, first, ADC2 + DAC
◎Digital data generator 8, digital human power pressure multiplier applied to DAC3 and digital data output from ADC2 will be explained.
By comparing the digital output voltage signal detected by the f:I unit 9, it is possible to perform characteristic tests on linearity, monotonous increase, offset, miss code, etc. of the ADC 2 and DAC 3.

次に交流特性の試験の場@−においては、ディジタルデ
ータ発生器8を計算機(図示していない)で制御し、デ
ィジタル交流波形を発生させ、DAC3に印加しADC
2のディジタル交流出力電圧信号音ディジタルデータ検
出器9で検出し、ディジタル信号処理装@(図示し、て
いない)でデータ処理を行ない、ADC2およびDAC
3の伝送損失周波数特性・伝送損失レベル特性および信
号対総会全電力比特性などの交流伝送特性をディジタル
信号の計算のみで行なうことができる。
Next, in the alternating current characteristic test site @-, the digital data generator 8 is controlled by a computer (not shown) to generate a digital alternating current waveform, which is applied to the DAC 3 and
The digital AC output voltage signal sound of No. 2 is detected by the digital data detector 9, and the data is processed by the digital signal processing device @ (not shown).
AC transmission characteristics such as transmission loss frequency characteristics, transmission loss level characteristics, and signal to total power ratio characteristics described in No. 3 can be calculated only by calculating digital signals.

〔発明の効果〕〔Effect of the invention〕

以上詳しく説明したように、本発明においては、ADC
およびDACk実際の使用状態に近い状態で変侯特性の
試験をすべてディジタル的手段で行なうことができるの
で、高、tgiのアナログ測定器は不要になる。またl
) A C3のアナログ出力端子7を短A結巌10でA
DQ2のアナログ入力端子4に接続し、で測定するので
、アナログ雑音が混入すること?抑1flJ L、、8
511足が確実容易に行なわれる。従って、半切1体集
積回路のように1チツプ上に形成されている場合におけ
る、ウェーハ段階の検査において特に有効である。
As explained in detail above, in the present invention, the ADC
and DACk Since the variation characteristics can be tested entirely by digital means under conditions close to the actual usage conditions, high TGI analog measuring instruments are no longer required. Also l
) A Connect analog output terminal 7 of C3 to A with short A connection 10
Since it is connected to analog input terminal 4 of DQ2 and measured, will analog noise be mixed in? Sup1flJ L,,8
511 feet are certainly easily performed. Therefore, it is particularly effective for inspection at the wafer stage when a half-cut integrated circuit is formed on one chip.

交流測定の場合には、複数イ固の周波数の信号音一度に
印加して測定することもでき、測定を迅速に行なうこと
ができる。
In the case of AC measurement, it is also possible to apply signal tones of a plurality of frequencies at once for measurement, and measurement can be carried out quickly.

なお本試験方法は実施例で説明したj:′)に、低レベ
ルで愉子化撮幅が小さい非線形特性の変換器の場合に特
に有用であるが、必ずしもそれに限定きれず線形特性の
場合にも適用できることはいうまでもない。
This test method is particularly useful for converters with non-linear characteristics that have a low level of j:') and a small range of variation, as explained in the example, but it is not necessarily limited to this, and can also be used in the case of linear characteristics. Needless to say, it is applicable.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例の回路ブロック図である。 1 ・・・ADQ DAC悟1戒像器、  2・・・ア
ナログ・ディジタル変換器3・・・ディンタル・アナロ
グ  4・・・アナログ入力端子、変換器(DAC)、 5・・・テイジタル出力端子、  6・・・ディジタル
入力端子、7・・・アナログ出力端子、   8・・・
ディジタルデータ発生器、9・・・テイジタルデータ検
出器、10・・・結線。
FIG. 1 is a circuit block diagram of an embodiment of the present invention. 1... ADQ DAC Satoru 1 imager, 2... Analog-digital converter 3... Digital analog 4... Analog input terminal, converter (DAC), 5... Digital output terminal, 6...Digital input terminal, 7...Analog output terminal, 8...
Digital data generator, 9... Digital data detector, 10... Connection.

Claims (1)

【特許請求の範囲】[Claims] 機器内に、アナグロ・ディジタル変換器とディジタル・
アナログ変換器がともに構成要素としてあるときの、前
記変換器の試験方法として、前記ディジタル・アナログ
変換器に前記アナログ・ディジタル変換器を縦続接続し
、前記ディジタル・アナログ変換器にディジタル入力信
号を入力し、前記アナログ・ディジタル変換器のディジ
タル出力信号をとりだし、上記ディジタル入力信号とデ
ィジタル出力信号との関係から、前記ディジタル・アナ
ログ変換器とアナログ・ディジタル変換器との特性を試
験することを特徴とするデータ変換器の試験方法。
There is an analog-to-digital converter and a digital converter in the device.
As a test method for the converter when both analog converters are included as constituent elements, the analog-to-digital converter is connected in cascade to the digital-to-analog converter, and a digital input signal is input to the digital-to-analog converter. and extracting the digital output signal of the analog-to-digital converter, and testing the characteristics of the digital-to-analog converter and the analog-to-digital converter from the relationship between the digital input signal and the digital output signal. Test method for data converters.
JP18096584A 1984-08-30 1984-08-30 Testing method of data converter Pending JPS6158323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18096584A JPS6158323A (en) 1984-08-30 1984-08-30 Testing method of data converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18096584A JPS6158323A (en) 1984-08-30 1984-08-30 Testing method of data converter

Publications (1)

Publication Number Publication Date
JPS6158323A true JPS6158323A (en) 1986-03-25

Family

ID=16092374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18096584A Pending JPS6158323A (en) 1984-08-30 1984-08-30 Testing method of data converter

Country Status (1)

Country Link
JP (1) JPS6158323A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS621324A (en) * 1985-06-27 1987-01-07 Toshiba Corp Evaluating method for linearity of digital-analog converter
JPS62286322A (en) * 1986-06-05 1987-12-12 Oki Electric Ind Co Ltd Data error detecting system by adpcm coding
JPH03145328A (en) * 1989-10-31 1991-06-20 Hitachi Ltd Analog and digital hybrid semiconductor integrated circuit
JP2011109653A (en) * 2009-10-26 2011-06-02 Fluke Corp Data acquisition system and calibration method therefor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS621324A (en) * 1985-06-27 1987-01-07 Toshiba Corp Evaluating method for linearity of digital-analog converter
JPS62286322A (en) * 1986-06-05 1987-12-12 Oki Electric Ind Co Ltd Data error detecting system by adpcm coding
JPH03145328A (en) * 1989-10-31 1991-06-20 Hitachi Ltd Analog and digital hybrid semiconductor integrated circuit
JP2011109653A (en) * 2009-10-26 2011-06-02 Fluke Corp Data acquisition system and calibration method therefor
US9671485B2 (en) 2009-10-26 2017-06-06 Fluke Corporation System and method for calibrating a high resolution data acquisition system with a low resolution digital to analog converter

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