JPS6158269A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve operational margin and speed by a method wherein semiconductor elements commonly driving an emitter and collector are arranged on specified positions. CONSTITUTION:A collector in the first conductive type regions 2 and the second conductive type region 3, an emitter in the second conductive regions 4 and a base in the first conductive type regions 5 ohmic-junctioned with the substrate 1 are easily formed on the first conductive substrate 1 by means of normal planar diffusion technology to integrate the collector and the emitter into a semiconductor cell S1 connected through the intermediary of load resistors 13. When base terminals 11 are impressed with specified bias voltage with similar semiconductor element cells S2 arranged at specified interval, the cells S1,S2 and respective collector and emitter connecting to terminals 14, 15 may be coupled with each other subject to the current controlled negative resistance characteristics. On the other hand, when the reverse polarity setting up voltage of terminals 14, 15 is inversed, a storage carrier near one collector may be shifted in the other collector side drift electric field to reduce the non-symmetry of electric coupling effect for increasing operational margin making elements S1 etc. turn OFF rapidly due to drifting effect.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a shift register and memory comprising a plurality of combinations of semiconductor elements having negative resistance characteristics.

The present invention relates to a semiconductor device capable of performing all functions such as a logic element.

(Prior art) A plasma-coupled device (plasma-coupled device) is used as a semiconductor device that combines conventional negative resistance characteristics.
ice)-(Patent No. 936522 2 Semiconductor device: Suzuki, Mizushima) has been proposed. As shown in Fig. 4, this device has a unijunction transistor with a hook as the front bottom of the basic electrode, and Fig. 4A is a plan view of the unit gate.
B shows its cross-sectional view.

In the figure, Ql is a unit semiconductor device, and 1 is the first 4′t
2 is a first region formed in the semiconductor substrate and has a second conductivity type; 3 is a first region formed in the first region 2173 and has a first conductivity type; 117) A second region 4 having a second conductivity type, 4 formed in the semiconductor substrate, facing the 117th region 2, and having a second conductivity type, 5 formed in the semiconductor substrate. , and a fourth region having the first conductivity type, and 6 represents a bias power source. However, under the bias conditions shown in FIG. 4, a semiconductor element Q+ exhibiting the negative resistance characteristic of the tortoise control type shown in FIG. 5 is inserted between the second region 3 and the third region 4 as a basic unit. It is used as a cell. When configuring a shift register, memory, etc., a large number of electrode groups are arranged on the same semiconductor substrate 1,
It utilizes the electrical coupling effect between each unit cell.

Figure 6 shows a specific example of a shift register, in which as soon as the input from the signal input line 10 is applied to the drive terminals 7 to 9, it is shifted from cell Q to Q, . . . in synchronization with the clock pulse shown in Figure 7. and can be transferred.

(Problems to be Solved by the Invention) The above is an overview of the structure and operating principle of a conventional plasma coupled device. However, with this configuration, it is difficult to increase the asymmetry of electrical coupling between each unit cell, and the device does not operate. It has disadvantages such as a small margin and a relatively slow transfer operating frequency of less than 10MHz.

(Ninth Means for Solving the Problems) The present invention was proposed to solve these problems, and its purpose is to provide a semiconductor device that can be easily manufactured using ordinary planar diffusion technology. do.

To achieve the above object, the present invention includes a first region having a second conductivity type formed in a semiconductor substrate having a first conductivity type, and a 7C10 region formed in the first region. a second region having a conductivity type; a third region formed within the semiconductor substrate and facing the first region and having a second conductivity type; and a third region formed within the semiconductor substrate and having a second conductivity type. A plurality of semiconductor elements each having a fourth region having a conductivity type of one conductivity type and having a unit cell having a configuration in which the second and third regions are electrically connected are formed using the semiconductor substrate in common. , the fourth region is under a constant bias, the first region is
a first connection terminal of the second and third regions of the semiconductor element;
The element group coupled to the terminal 9 exhibiting negative resistance characteristics with the second connection terminal of at least one other adjacent semiconductor element is capable of receiving carrier injection due to the turn-on state of the set of semiconductor elements. and at least one other semiconductor element adjacent to said first semiconductor element, maintaining a distance from each other such that a sufficient relationship is obtained such that the turn-on voltage of said first semiconductor element and at least one other semiconductor element adjacent to said first semiconductor element is reduced based on a change in fcit level through a bulk resistor. The gist of the invention is a semiconductor device characterized in that it is arranged as follows.

Next, the present invention will be explained in detail. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

FIG. 1 shows an embodiment of the present invention, in which A shows a plan view of a basic cell of the invention, and B shows a sectional view thereof. In the figure l
2 is a semiconductor substrate containing a first conductivity type; 2 is a first region formed in the semiconductor substrate and has a second conductivity type; 3
is formed in the first region 2FE3 and has a first conductivity type; 4 is formed in the semiconductor substrate, faces the first region 2, and has a second conductivity type; a third region 5 having a 4-electrode type is formed in the semiconductor substrate;
and a fourth region having the first conductivity type. Thus, the third region 4 serves as an emitter for injecting minority carriers, the fourth region 5 serves as a base for making an ohmic contact with the semiconductor substrate, and the first region 2 and the second region Region 3 serves as a hook junction collector electrode. However, the emitter and collector have a load resistance of 13
It is connected by wiring through. 14 indicates a common terminal between the emitter and the collector. This is called cell S. Ma'f
By arranging the cell S having the same electrode configuration as cs and adjacent to the cell s1, an fcW coupling effect, which has not been previously obtained, can be obtained between the cells. Note that 15 indicates the common terminal of the emitter and collector of cell S. That is, if the pace electrode terminal 11 is set to a constant bias (for example, 5V) with respect to the reference voltage (for example, OV), the terminal 14 is set to H-level (for example, 6V), and the terminal 15 is set to L-level (for example, OV). , between terminals 14 and 15, terminal 14
However, a current flows to the terminal 15, and a negative resistance characteristic of the current control type as shown in FIG. 5 is generated. That is, with the above level setting, only the cell S, the emitter and the collector of the cell s2 are in the forward direction, while the other electrodes, the collector of the cell sl and the emitter of the cell S are in a cut-off state. Naturally, if the level settings of cells S and 82 are reversed, negative resistance characteristics of the current control type flowing in the opposite direction will be exhibited.

With this configuration, the levels of terminals 14 and 15 are changed from H to L.
, L-+HK are inverted, the minority carriers accumulated near the collector electrode of cell s2 move to the collector side of cell Sl due to the drift electric field, resulting in a higher switching rate than in the case without the drift effect. / Off time becomes extremely short. Moreover, by utilizing the presence or absence of carriers due to the drift, it is possible to increase the asymmetry of the electrical coupling effect.

FIG. 2 shows a planar pattern of an embodiment of the two-phase drive shift register of the present invention, and shows the case where no resistor is inserted between the emitter and collector, but a resistor can be added as necessary. In this structure, the emitter and collector are arranged in a t-meander shape, and the shape is asymmetric, so that an asymmetrical effect of large coupling can be obtained. In the figure, 7 and 8 are drive terminals, 10 is a signal input line, and 16 is a potential detection electrode (fifth region having the first conductivity type). To drive this shift register, each pulse shown in the timing chart of FIG.
It is sufficient to apply the voltage to drive terminals 8 and 7, respectively. The pulse D is transferred to the right in FIG. area), etc. can be defeated. Now, the collector of cell S1 is at L- level, and the level of signal input i10 is at H- level.
In a state where minority carriers are injected at the cell S, minority carriers are accumulated around the collector of the cell S (state at time t in FIG. 3). However, the collector of cell S is H.
- level, and when the collector of cell S becomes L- level (state at time t in Fig. 3), the above accumulated carriers are affected by the drift effect of the electric field strength, which is caused by the amplitude difference between pulses E and F. Move from cell S to cell S2 to speed up the cutoff operation. Furthermore, these triad carriers are injected from the emitter of cell S and join the friend carriers, resulting in rapid conduction, realizing high-speed switching, and imparting asymmetry to the electrical coupling effect between adjacent cells. . Not only the asymmetrical effect of the collector and emitter electrode shapes, but also the asymmetrical effect of the electric drive means using two-phase drive, it is possible to obtain a large operating margin, and the configuration of the two-phase drive shift register is It becomes easier. In particular, the drift field effect becomes more pronounced as the distance between collector electrodes within a unit cell becomes smaller, and narrowing the cell pitch is also advantageous for high-speed operation.

Although the above description is about a two-phase drive shift register, it goes without saying that it is also applicable to three-phase drive, and can also be applied to configurations of various other logical functions. Further, as for the operating voltage, an example in which the bias voltage is 5V has been described, but since the operating margin can be made larger than that of a conventional plasma coupled device, even lower voltage operation is possible, and power consumption can be reduced.

(Effect of the invention) Above 89. As explained above, according to the present invention, by driving the emitter and collector electrodes in common, the operating margin is increased compared to the conventional case where the collector is fixed, and the carrier transport effect based on the drift electric field is High-speed switching operation is possible.

Since the 'fc\mf''I'' margin can be increased, a two-phase drive shift register, which was difficult to realize with the conventional structure, can be easily constructed, and the wiring area can also be narrowed, which is advantageous for high density and large capacity. Furthermore, since the configuration of the drive pulse is simple, the peripheral circuitry can be simplified, and the overall effect is excellent as a basic element suitable for high-speed, high-density LSI integrated circuits.

[Brief explanation of drawings]

1, 2, and 3 are diagrams showing the principle and structure of a semiconductor device according to the present invention, and FIG. 1A is a plan view of a unit cell, and FIG.
2 is a sectional view thereof, FIG. 2 is a plan view of an embodiment of the shift register, and FIG. 3 is a timing chart of drive pulses for driving the shift register. 4, 5, 6, and 7 are diagrams of conventional plasma coupled devices containing water, and FIG. 4A is a plan view of a unit gate;
FIG. 4B is a sectional view thereof, FIG. 5 is a characteristic curve diagram of a unit gate, FIG. 6 is a schematic plan view of the entire device, and FIG. 7 is a pulse timing chart for driving the device. l...Semiconductor substrate 2...First box area 3...Second area 4...・Third region 5...Fourth region 6...Bias ta Q,...Semiconductor device 7.8.9 ...Drive terminal lO...Signal input line 11...Common pace electrode terminal 12...
......Common collector electrode 13...
Load resistance 14... Emitter 4 and collector (2,!
:3) O common terminal 15...,..., emitter and collector common terminal 16...Fifth region (potential detection electrode) Q
, ~Q4...Unit semiconductor device R1-R4...Load resistance S5, Ss...Unit cell

Claims (4)

[Claims] (1) A first region having a second conductivity type formed in a semiconductor substrate having a first conductivity type, and a second region having a first conductivity type formed within the first region. a third region formed in the semiconductor substrate, facing the first region and having a second conductivity type; and a third region formed in the semiconductor substrate having the first conductivity type. A plurality of semiconductor elements having a unit cell having a configuration in which the second and third regions are electrically connected are formed using the semiconductor substrate in common, and the fourth region is a negative voltage between the first connection terminal of the second and third regions of the first semiconductor element and the second connection terminal of at least one other adjacent semiconductor element under a constant bias. A group of elements coupled so as to exhibit a resistive characteristic is connected to the first semiconductor element and another adjacent semiconductor element based on the carrier injection caused by the turn-on state of the set of semiconductor elements and the potential change via the bulk resistance. A semiconductor device characterized in that the semiconductor devices are arranged at a distance from each other so as to obtain a sufficient relationship to reduce the turn-on voltage of at least one other semiconductor device. (2) In the semiconductor device according to claim 1,
A semiconductor device characterized in that a second region and a third region are connected through a resistor. (3) In the semiconductor device according to claim 1,
A semiconductor device, wherein the plurality of semiconductor elements are sequentially arranged in a predetermined arrangement direction, and each of the plurality of semiconductor elements has an emitter and a collector arranged in a meandering shape and has an asymmetric shape. (4) In the semiconductor device according to claim 1,
A semiconductor device characterized in that a fifth region having a first conductivity type is provided for detecting a turn-on or turn-off state of the semiconductor element.