JPS6157530U - - Google Patents
Info
- Publication number
- JPS6157530U JPS6157530U JP1984141306U JP14130684U JPS6157530U JP S6157530 U JPS6157530 U JP S6157530U JP 1984141306 U JP1984141306 U JP 1984141306U JP 14130684 U JP14130684 U JP 14130684U JP S6157530 U JPS6157530 U JP S6157530U
- Authority
- JP
- Japan
- Prior art keywords
- groove
- lead frame
- semiconductor
- molded block
- resin molded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000000465 moulding Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図および第２図は本考案の実施例を示し、
第１図はこの実施例の一部切欠斜視図、第２図は
その縦断側面図、第３図は成型金型を示す縦断面
図、第４図は従来例を示す一部切欠平面図、第５
図はその側面図である。
１…半導体チツプ、２…リードフレーム、５…
リード端子、７…樹脂成型ブロツク、８…樹脂成
型ブロツクの外面、９…溝。
1 and 2 show an embodiment of the present invention,
FIG. 1 is a partially cutaway perspective view of this embodiment, FIG. 2 is a longitudinal sectional side view thereof, FIG. 3 is a longitudinal sectional view showing a molding die, and FIG. 4 is a partially cutaway plan view showing a conventional example. Fifth
The figure is a side view thereof. 1... Semiconductor chip, 2... Lead frame, 5...
Lead terminal, 7... Resin molded block, 8... Outer surface of resin molded block, 9... Groove.
Claims (1)
とを備え、該リードフレームに形成された複数の
リード端子をそれぞれ半導体チツプに接続すると
ともに、該半導体チツプとリードフレームとを樹
脂モールドにより一体にパツケージングしてなる
半導体装置において、前記樹脂モールドにより形
成された樹脂成型ブロツクの外面に、これの成型
時に発生する内部応力を緩和する溝を形成したこ
とを特徴とする半導体装置。 (2) 前記実用新案登録請求の範囲第１項に記載
の半導体装置において、前記溝が前記樹脂成型ブ
ロツクの上下両面に周回状に形成されている半導
体装置。[Claims for Utility Model Registration] (1) A semiconductor chip and a metal lead frame, each of which has a plurality of lead terminals formed on the lead frame connected to the semiconductor chip; and a semiconductor device integrally packaged by a resin mold, characterized in that a groove is formed on the outer surface of the resin molded block formed by the resin mold to relieve internal stress generated during molding. Semiconductor equipment. (2) The semiconductor device according to claim 1, wherein the groove is formed in a circumferential manner on both upper and lower surfaces of the resin molded block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984141306U JPS6157530U (en) | 1984-09-18 | 1984-09-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984141306U JPS6157530U (en) | 1984-09-18 | 1984-09-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6157530U true JPS6157530U (en) | 1986-04-17 |
Family
ID=30699649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984141306U Pending JPS6157530U (en) | 1984-09-18 | 1984-09-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6157530U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5460564A (en) * | 1977-10-24 | 1979-05-16 | Hitachi Ltd | Resin mold semiconductor device |
-
1984
- 1984-09-18 JP JP1984141306U patent/JPS6157530U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5460564A (en) * | 1977-10-24 | 1979-05-16 | Hitachi Ltd | Resin mold semiconductor device |