JPS6156977A - Fault detector - Google Patents

Fault detector

Info

Publication number
JPS6156977A
JPS6156977A JP59177428A JP17742884A JPS6156977A JP S6156977 A JPS6156977 A JP S6156977A JP 59177428 A JP59177428 A JP 59177428A JP 17742884 A JP17742884 A JP 17742884A JP S6156977 A JPS6156977 A JP S6156977A
Authority
JP
Japan
Prior art keywords
circuit
voltage
semiconductor elements
semiconductor
snubber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59177428A
Other languages
Japanese (ja)
Other versions
JPH0339633B2 (en
Inventor
Katsuro Ito
克郎 伊藤
Yukio Watanabe
幸夫 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59177428A priority Critical patent/JPS6156977A/en
Publication of JPS6156977A publication Critical patent/JPS6156977A/en
Publication of JPH0339633B2 publication Critical patent/JPH0339633B2/ja
Granted legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

PURPOSE:To enable the detection of a fault in a semiconductor element or a non-linear type resistance without malfunctioning in a short time after the stoppage of the operation, by checking the voltage of a bridge circuit with all semiconductor elements turned on in a specified period immediately after the operation of a voltage adjusting circuit is stopped. CONSTITUTION:Immediately after the opration of a voltage adjusting circuit 1 is stopped, a pulse is sent from a one-shot multivibrator circuit 15 triggered at the down edge for a specified period to turn ON all of semiconductor elements 21- 24. At this point, charges of snubber capacitors 41-44 are discharged through snubber resistances 31-34 to reduce the shared voltages thereof to zero equally. So, when the elements 21-24 are turned OFF simultaneously, a bridge circuit keeps the balance thereof if the semiconductor elements 21-24 and non-linear resistances 51-54 are all sound, making the output of a voltage detection circuit 7 zero. Any abnormality in the elements 21-24 or resistances 51-54 will break the balance of the bridge circuit. Thus, the circuit 7 can detect a fault.

Description

【発明の詳細な説明】 〔発明の技術的分野〕 本発明は半導体素子と非線形抵抗体を並列に接続した回
路を複数個直列に構成した電圧調整回路の半導体素子あ
るいは非線形抵抗体の故障、検出装置に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to failure and detection of a semiconductor element or a nonlinear resistor in a voltage regulating circuit configured in series with a plurality of circuits in which a semiconductor element and a nonlinear resistor are connected in parallel. Regarding equipment.

〔発明の技術的背景とその問題点〕   。[Technical background of the invention and its problems].

□ 半導体素子と非線形抵抗体を並列に接続17た回路
を複数個直列に構成し、半導体素子のオと・・オフ制御
により回路の電圧降下を利用して電・圧調整を行なうこ
とが出来る0第3図はそ、の様′な電圧調整回路のブロ
ック図であり、第41図はタイミングチャートである。
□ Multiple circuits in which semiconductor elements and nonlinear resistors are connected in parallel17 are configured in series, and the voltage drop in the circuit can be used to adjust the voltage by controlling the semiconductor elements on and off. FIG. 3 is a block diagram of such a voltage regulating circuit, and FIG. 41 is a timing chart.

図において1は電圧調整回路、21〜24は半導体素子
、31〜34はスナバ抵抗、4−1〜44はスナバコン
デンサ、51〜54・は些線形抵抗、’61.62は分
圧用抵抗、7は電圧検出回路、8は直流電源、9は、負
荷抵抗であり10は・半導体制御回・路、11はタイム
ディレィ回路、’12.11インバτり、13はアンド
回路である。
In the figure, 1 is a voltage adjustment circuit, 21 to 24 are semiconductor elements, 31 to 34 are snubber resistors, 4-1 to 44 are snubber capacitors, 51 to 54 are trivial linear resistors, '61.62 are voltage dividing resistors, 7 8 is a voltage detection circuit, 8 is a DC power supply, 9 is a load resistor, 10 is a semiconductor control circuit, 11 is a time delay circuit, '12.11 inverter τ, and 13 is an AND circuit.

aは運転信号、b・は故障検出信号であり、a′・は久
・イ・ムディレイ回路11の出力である。
a is an operating signal, b is a failure detection signal, and a' is an output of the delay circuit 11.

第3図で半導体素子21〜24はオフし、ているとする
と直流電源8の電流は、非−形抵抗31〜34を介して
負荷抵抗9に流入する。この時負荷抵抗9に流入する電
流!・Lは、直流電源8の%圧をE1非腺形抵抗51〜
54の制限電圧を名々■、負荷抵抗9の抵抗値をRL 
 とすれば、TL = (E  4 v )/ RL 
となる0ここで半導体素子2ノをオンすると負荷電流■
L  けIL = (Ei −3v ) / Ry、と
なる。この様に負荷電流■L  を増加する特番」、半
導体素子を順次オン17、また、負荷電流IL  を減
少する時にはオンしている半導体素子をオフすることに
より負荷電流IL  の制御が可能となる。この制御を
行なうのが半導体制御回路10である。
Assuming that the semiconductor elements 21-24 are off in FIG. 3, the current from the DC power supply 8 flows into the load resistor 9 via the non-conducting resistors 31-34. At this time, the current flowing into the load resistor 9!・L is the % pressure of the DC power supply 8. E1 non-glandular resistor 51 ~
The limiting voltage of 54 is named ■, and the resistance value of load resistor 9 is RL.
Then, TL = (E 4 v)/RL
0Here, when semiconductor element 2 is turned on, the load current becomes ■
L = (Ei - 3v) / Ry. In this way, the load current IL can be controlled by sequentially turning on the semiconductor elements 17 in order to increase the load current IL, and by turning off the semiconductor elements that are on when decreasing the load current IL. The semiconductor control circuit 10 performs this control.

ま7)半導体素子21〜24、あるいは非直線抵抗体5
1 = 54の故障を検出するために、直列接続された
分圧用抵抗61.62を電圧調整回路に並列に接続して
、ブリッジを構成し、電、、   FF′m *rm 
wr x、“5+ E @Wrf)G k f) m 
r’dl !”5′リッジ回路の出力電圧を得て、この
電圧を電圧検出回路7で検出し、半導体素子21〜24
の故障を検出している。
7) Semiconductor elements 21 to 24 or nonlinear resistor 5
1 = 54 faults, voltage dividing resistors 61 and 62 connected in series are connected in parallel to the voltage adjustment circuit to form a bridge, and the voltage, FF′m *rm
wr x, “5+ E @Wrf)G k f) m
r'dl! The output voltage of the ``5'' ridge circuit is obtained, this voltage is detected by the voltage detection circuit 7, and the semiconductor elements 21 to 24 are detected.
is detecting a failure.

即ち、非線形抵抗51〜54はそれぞれほぼ同一の値で
あり、又、分圧用抵抗61と62はほぼ同一・の値、ス
ナバ抵抗31〜34も同一の値、スナバコンデン941
〜44も同一の値であるので、半導体素子と、非線形抵
抗が正常であれば、ブリッジ回路の出力堵:圧はほぼ零
であるが、半導体素子21、あるいPi Jli紛形成
形抵抗51障I7、短絡状態となると、ブリッジ回路の
平衡が失なわれ、電圧検出回路7で検出できる。なお、
当然のことながら故障検出は半2#体素子21・〜24
がオフ状態の時に行なわなければならない。
That is, the nonlinear resistors 51 to 54 have approximately the same value, the voltage dividing resistors 61 and 62 have approximately the same value, the snubber resistors 31 to 34 also have the same value, and the snubber capacitor 941 has the same value.
~44 are the same value, so if the semiconductor element and the nonlinear resistance are normal, the output pressure of the bridge circuit is almost zero, but if the semiconductor element 21 or the Pi Jli powder resistor 51 is faulty. When I7 becomes short-circuited, the balance of the bridge circuit is lost, which can be detected by the voltage detection circuit 7. In addition,
Naturally, failure detection is performed by semi-2# body elements 21 to 24.
This must be done when the is in the off state.

しかし、今、第4図に示す様に本電圧調整回路をT、か
らT、までの期間運転し時刻T、ですべての半導体素子
をオフ状態とし運転を停止したとしても、運転中である
時刻T、  の直前輻電圧調整のためすべての半導体素
子がオン状態、あるいはオフ状態にあるとはかぎらず、
各々の半導体素子の電圧分担が異なっている。従ってす
べての半導体素子21〜24あるいは非線形抵抗体51
〜54が正常であっても、運転停止時刻T、  直後は
、スナバロンデンf−41〜44にたくわ見られている
電荷量の相異からブリッジ回路の平衡が失なわれ、ブリ
ッジ回路の出力電□圧が零とならず、故障であると判定
する可能性がある。スナバコンデンサ41〜44の電荷
の放電はスナバ回路と並列に接続されている工、L/メ
ントのインピーダンスが大キく、放電時定数が大きくな
るので誤まりのない故障検出を行なうためにはタイムデ
ィレィ回路11の遅延時間を数分以上にしなければなら
ないという欠点が□あった。
However, as shown in Fig. 4, even if this voltage adjustment circuit is operated for a period from T to T and all semiconductor elements are turned off at time T and the operation is stopped, even if Due to the immediate voltage adjustment of T, not all semiconductor elements are necessarily in the on or off state,
The voltage sharing of each semiconductor element is different. Therefore, all the semiconductor elements 21 to 24 or the nonlinear resistor 51
Even if F-54 is normal, immediately after the operation stop time T, the balance of the bridge circuit will be lost due to the difference in the amount of charge that is often observed in Snubber Ronden F-41 to F-44, and the output voltage of the bridge circuit will decrease. □There is a possibility that the pressure will not become zero and it will be determined that there is a failure. When discharging the charges of the snubber capacitors 41 to 44, the impedance of the capacitors connected in parallel with the snubber circuit is large, and the discharge time constant becomes large. There was a drawback that the delay time of the delay circuit 11 had to be several minutes or more.

〔発明の目的〕[Purpose of the invention]

゛従って本発明の目的は、前述の点に艦みなさ□れたも
のであって、運転中の半導体素子の状態が□いかなる状
態であっても、運転停止後短時間のうちに誤動作のない
半導体素子あるいは゛非線形抵抗体の故障を検出出来る
故障検出装置を提供す□ることにある。    □ ゛ 〔発明の概要〕 本発明はこの目的を達成するために、電圧調整回路の運
転停止後、休止期間中にただちに電圧調整回路の全半導
体素子を所定の期間オンし、スナバコンデンサにたくわ
見られた電荷量を短時間のうちに等しくし、運転停止後
短時間で誤動作することなく半導体素子あるいは非線形
抵抗の故障を判別できる様にしたことを特徴とするもの
である。
Therefore, an object of the present invention is to solve the above-mentioned points, and to provide a semiconductor device that does not malfunction within a short period of time after the operation is stopped, regardless of the state of the semiconductor device during operation. The object of the present invention is to provide a failure detection device that can detect failures in elements or nonlinear resistors. □ ゛ [Summary of the Invention] In order to achieve this object, the present invention turns on all the semiconductor elements of the voltage regulation circuit for a predetermined period immediately during the rest period after the voltage regulation circuit stops operating, and stores it in the snubber capacitor. This is characterized in that the observed charge amounts are equalized within a short time, so that failures in semiconductor elements or nonlinear resistors can be determined without malfunction within a short time after the operation is stopped.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例を第1図に示す。第1図に゛おいて第
3図と同一機能を有するものは同一番号とし説明は省略
する。
An embodiment of the present invention is shown in FIG. Components in FIG. 1 having the same functions as those in FIG. 3 are designated by the same numbers, and descriptions thereof will be omitted.

第1図において15はダウンエツジでトリガされるワン
ショット回路であり、14.16はOR回路である。
In FIG. 1, 15 is a one-shot circuit triggered by a down edge, and 14 and 16 are OR circuits.

第2図は本発明の動作を表すタイミングチャートである
FIG. 2 is a timing chart showing the operation of the present invention.

以下、第1図、第2図により本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 and 2.

今、第1図の電圧調整回路Jを運転信号aにより第2図
に示される様にT。からT、までの時刻・動作させたと
する。TO”TI  までの期間は電圧調整を行なって
いるので、半導体素子21〜24はどの素子がONでど
の素子がOFFであるか、はわからず、運転停止時刻T
、の直後は各々の半導体素子の分担電圧は異なっている
と考えられる。そこで時刻T、の直後時刻T2  から
T、までの所定の期間ダウンエツジでトリガされるワン
ショット回路15によりパルスを出1〜、電圧調整回路
1のすべての半導体素子21〜24をオン状態とする。
Now, the voltage adjustment circuit J of FIG. 1 is turned to T as shown in FIG. 2 by the operation signal a. Assume that the time and operation are from to T. Since the voltage is adjusted during the period up to TO''TI, it is not known which semiconductor elements 21 to 24 are ON and which are OFF, and the operation stop time T
Immediately after , it is considered that the shared voltages of each semiconductor element are different. Therefore, the one-shot circuit 15 which is triggered by the down edge for a predetermined period from time T2 to time T, immediately after time T, outputs a pulse 1 to turn on all the semiconductor elements 21 to 24 of the voltage adjustment circuit 1.

時刻T2  で半導体素子21〜24がオン状態となる
と、スナバ抵抗31〜34を介してスナバコンデンサ4
1〜44の電荷が放電され百μs@度でスナバコンデン
サ41〜44の分担電圧は等しく零となる。そこで時刻
T3  で、半導体素子21〜:、     24を一
斉にオフすれば、半導体素子21〜24と非線形抵抗5
1〜54がすべて健全であればブリッジ回路は平衡を保
ち、電圧検出回路7は出力零であり、もし、半導体素子
21〜24あるいは非線形抵抗51〜54に異常が存在
するならば、ブリッジ回路の平衡がくずれ、電圧検出回
路7は、故障を検出することができる。従って、電圧検
出回路7の出力を時刻T3以降とりこむことにすれば誤
まりのない故障検出信号bl得ることができる。T2ヘ
ーT、までの期間はスナバ抵抗とスナバコンデンサによ
る時定数から、スナバコンデンサが十分に放電できる時
間をとる梯にすればよい。
When the semiconductor elements 21 to 24 are turned on at time T2, the snubber capacitor 4 is turned on via the snubber resistors 31 to 34.
The charges 1 to 44 are discharged and the shared voltages of the snubber capacitors 41 to 44 equally become zero in 100 μs@degree. Therefore, at time T3, if the semiconductor elements 21 to 24 are turned off all at once, the semiconductor elements 21 to 24 and the nonlinear resistance 5 are turned off.
If all 1 to 54 are healthy, the bridge circuit is balanced and the voltage detection circuit 7 has zero output. If there is an abnormality in the semiconductor elements 21 to 24 or the nonlinear resistors 51 to 54, the bridge circuit will be in balance. If the balance is lost, the voltage detection circuit 7 can detect the failure. Therefore, if the output of the voltage detection circuit 7 is taken in after time T3, a failure detection signal bl without error can be obtained. The period from T2 to T may be set to a ladder that allows sufficient time for the snubber capacitor to discharge from the time constant of the snubber resistor and the snubber capacitor.

第1図においCり1′ムデイレ・イ回路1ノをはぶL’
rI とT2  の期間は零とおいてもよい。
In FIG.
The periods rI and T2 may be set to zero.

また、電圧調整回路と、負荷抵抗の間にスイッチを設は
半導体素子21〜24をすべてオンするT、−T3の期
間のみ、回路電流をバイパスするか、あるいは高抵抗を
電圧調整回路と負荷の間に設けることによ;1バ停止期
間中に負荷に大電流を流すことをさけることができる。
In addition, by installing a switch between the voltage adjustment circuit and the load resistor, the circuit current can be bypassed only during periods T and -T3 when all the semiconductor elements 21 to 24 are turned on, or a high resistance can be installed between the voltage adjustment circuit and the load. By providing this in between, it is possible to avoid flowing a large current to the load during one bar stop period.

〔発明の効果〕〔Effect of the invention〕

以上の説明の樺に本発明によれば、電圧調整回路を運転
停止後、ただちに所定の期間全半導体素子をオンした後
にブリッジ回路の電圧を検出することにより、運転停止
後短時間のうちに誤動作のない半導体素子、あるいけ非
線形抵抗の故障検出を行なうことができる。
In contrast to the above explanation, according to the present invention, by detecting the voltage of the bridge circuit after turning on all the semiconductor elements for a predetermined period immediately after the voltage regulating circuit is stopped, malfunction occurs within a short time after the operation is stopped. It is possible to detect failures in semiconductor devices that do not have high resistance or nonlinear resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

、 第1図は本発明による電圧調整回路の故障検出回路
の一実施例を示すブロック図、第2図はそのタイミング
チャート、第3図は半導体素子と非線形抵抗体を並列に
接続した従来の電圧調整回路の故障検出回路の一実施例
を示、すブロック図、第4図はM3図の動作を説明する
だめのタイムチャートである。 1・・・電圧調整回路、21〜24・・・半導体素子、
31〜34・・・スナバ抵抗、41〜441°スナバコ
ンデンサ、51〜54・・・非線形抵抗体、61〜62
・・・分圧用抵抗、7・・・電圧検出回路、8・・・直
流電源、9・・・負荷抵抗、10・・・半導体制御回路
、11°・・タイムディレィ回路、12・・・インバー
タ、ノ4・・・OR回路、J5・・・ワンショット回路
、16・・・OR回路。
, Fig. 1 is a block diagram showing one embodiment of the failure detection circuit of the voltage regulating circuit according to the present invention, Fig. 2 is its timing chart, and Fig. 3 is a diagram showing a conventional voltage control circuit in which a semiconductor element and a nonlinear resistor are connected in parallel. FIG. 4 is a block diagram showing one embodiment of the failure detection circuit of the adjustment circuit, and is a time chart for explaining the operation of the M3 diagram. 1... Voltage adjustment circuit, 21-24... Semiconductor element,
31-34...Snubber resistor, 41-441° snubber capacitor, 51-54...Nonlinear resistor, 61-62
...Voltage dividing resistor, 7...Voltage detection circuit, 8...DC power supply, 9...Load resistor, 10...Semiconductor control circuit, 11°...Time delay circuit, 12...Inverter , No4...OR circuit, J5...one shot circuit, 16...OR circuit.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子とスナバ−回路及び非線形抵抗素子を並列に
接続した回路を複数個直列に構成した電圧調整回路と該
電圧調整回路に並列に接続される一対の分圧用抵抗から
成る直列回路とでブリッジ回路を構成し、前記電圧調整
回路と直列回路の中間点からブリッジ回路の出力電圧を
得て、前記半導体素子あるいは非線形抵抗体の故障を検
出するようにした故障検出装置において、前記電圧調整
回路の運転停止後又は運転期間の最後に所定期間前記電
圧調整回路の全半導体素子を導通状態にする手段を具備
した故障検出装置。
A bridge circuit consists of a voltage adjustment circuit configured in series with a plurality of circuits in which a semiconductor element, a snubber circuit, and a nonlinear resistance element are connected in parallel, and a series circuit consisting of a pair of voltage dividing resistors connected in parallel to the voltage adjustment circuit. In the failure detection device, the output voltage of the bridge circuit is obtained from an intermediate point between the voltage adjustment circuit and the series circuit, and a failure of the semiconductor element or the nonlinear resistor is detected. A failure detection device comprising means for bringing all semiconductor elements of the voltage regulating circuit into conduction for a predetermined period after stopping or at the end of an operating period.
JP59177428A 1984-08-28 1984-08-28 Fault detector Granted JPS6156977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59177428A JPS6156977A (en) 1984-08-28 1984-08-28 Fault detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59177428A JPS6156977A (en) 1984-08-28 1984-08-28 Fault detector

Publications (2)

Publication Number Publication Date
JPS6156977A true JPS6156977A (en) 1986-03-22
JPH0339633B2 JPH0339633B2 (en) 1991-06-14

Family

ID=16030760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59177428A Granted JPS6156977A (en) 1984-08-28 1984-08-28 Fault detector

Country Status (1)

Country Link
JP (1) JPS6156977A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6467171A (en) * 1987-09-05 1989-03-13 Ekushimu Shokai Kk Apparatus for applying twist pleat to bun or such
KR100435348B1 (en) * 2000-11-24 2004-06-10 레온 지도키 가부시키가이샤 Method and apparatus for forming creases on a piece of dough

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6467171A (en) * 1987-09-05 1989-03-13 Ekushimu Shokai Kk Apparatus for applying twist pleat to bun or such
JPH0420586B2 (en) * 1987-09-05 1992-04-03 Ekushimu Shokai Kk
KR100435348B1 (en) * 2000-11-24 2004-06-10 레온 지도키 가부시키가이샤 Method and apparatus for forming creases on a piece of dough

Also Published As

Publication number Publication date
JPH0339633B2 (en) 1991-06-14

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