JPS6156600B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides voltage divider properties between a voltage holding terminal and two terminals placed close to each other on both sides of the voltage holding terminal. The present invention relates to a voltage holding device that can increase the discharge time constant of accumulated charge in a capacitor.

As a simple voltage holding circuit, a signal peak value (hereinafter referred to as peak) detection circuit as shown in FIG. 1 is often used. In Figure 1, 1 is a signal source, 2 is a detection diode, 3 is a voltage holding charge/discharge capacitor,
4 is a buffer emitter follower transistor that transmits the held voltage to subsequent circuits. 5 is an emitter resistance of an emitter follower transistor, 6 is a holding voltage output, 7 is a reference power supply voltage terminal, 8 is a reference ground potential terminal, and 9 is a DC bias on the signal source side.

It is well known that when the signal from the signal source is a pulse signal as shown in FIG. 2a, a waveform as shown in FIG. 2b appears at the output terminal 6. The characteristic equation for the output voltage at this time is expressed by a capacitor charging/discharging equation as shown in equation (1).

V=V _P exp (-1/CRt) ...(1) However, R=Zin×Z _R /Zin+Z _R V _P = Pulse waveform peak voltage value (V) t = Next pulse input after starting discharge (sec) C = capacitor capacity (F) R = impedance seen from the capacitor connection terminal (Ω) Zin = buffer transistor input impedance Z _R = diode reverse leak resistance impedance Generally voltage When the holding capacity is large, V=
This means that V _P , and by increasing C in formula (1), we aim to improve its ability.

However, with today's trends toward smaller and lighter equipment, increasing the capacitance of capacitors means using electrolytic capacitors, which poses a major problem in terms of the area occupied on the printed circuit board. For example, in Fig. 1, the peak value of the signal input waveform is 1.7V, the resistance value R _E of the emitter resistor 5 of the emitter follower transistor 4 is 1KΩ, the h _FE of the emitter follower transistor 4 is 100, and the pulse period is Assuming 1/60 sec, let's look at the case where the voltage holding capacity is within V _P -V = 1 mV. Equation (2) for deriving the value of capacitor C from Equation (1) can be obtained as follows.

Normally, under a reverse voltage of Z _R = 1V, it can be considered to be 10 ¹² (Ω) or more. Zin is approximately R _E (h _FE +
1) If it is approximately 100KΩ, the value of capacitor C is becomes. A capacitor of 166 μF has not been realized even in the small, large-capacity models such as tartar electrolytic capacitors and chip capacitors that are currently being commercialized, and this is an extremely disadvantageous factor from the point of view of downsizing. So, for example, if you want to use a value of 0.16μF that can be realized as a chip capacitor, set R to 100MΩ.
If the setting is not made above, it will not be possible to ensure performance within 1 mV of voltage holding capacity. In the circuit configuration shown in FIG. 1, it is possible to increase the R component by using an element whose input impedance Zin is 100 MΩ or more, such as a FET, as the buffer transistor 4. As an example, as shown in Figure 3, if we consider a circuit in which circuit components other than the capacitor are incorporated as an integrated circuit as an extension of the trend toward miniaturization, leaks between the terminals of the package, leaks between the terminals on the printed circuit board, etc. Leakage etc. becomes a value that cannot be ignored. Also, it is difficult at present to desire a capacitor leak resistance of about 100MΩ or more.

In FIG. 3, 10 is a buffer stage not limited to emitter follower transistors, which is an element or circuit configuration whose input impedance can be theoretically considered to be infinite; 11 is a leak resistance of a capacitor; and 12 is connected to an integrated circuit device. A connection terminal for an external capacitor; 13 is a connection terminal for a functional element including the integrated circuit device adjacent to the capacitor terminal 12; 14 is another connection terminal adjacent to the capacitor terminal 12; 15 is each of the terminals 12; ，
13 is a leak resistance between the terminals 14 and 12, and 16 is a leak resistance between the terminals 14 and 12.

It is said that the leak resistance value between terminals should be 1MΩ to 2MΩ, taking into account moisture and dust when the integrated circuit device is inserted into the printed circuit board. Now, if both of the terminals 13 and 14 are significantly higher than the voltage held by the terminal 12 (for example, close to the power supply voltage) or close to the ground potential, the impedance seen from the terminal 12 will be due to capacitor leakage. This is equivalent to inserting 1MΩ to 2MΩ in parallel with the resistor. If R = 1MΩ and calculation is performed using equation (1), V = V _P exp (-1/CRt) = 1 x exp (-1/60 x 1/0.16 x 10 ^-6
×10 ⁶ ) = 0.901 V _P -V = 99 (mV) The voltage holding ability drops by 10% to 99 (mV), and the requirement that V _P -V = 1 mV or less cannot be satisfied. The present invention solves the above-mentioned problems, and will be explained in detail with reference to the embodiment shown in FIG.

The device shown in FIG. 4 is inserted between adjacent terminals of a capacitor 3 in contrast to the device shown in FIG. 3 described above.

This device reduces the influence of terminal leak resistance by imparting voltage divider properties between adjacent terminals 13 and 14.

In other words, in this device, the potential of the terminal 14 is selected to be higher than the potential to be held at the terminal 12,
On the other hand, the potential of the terminal 13 should be selected to be low, contrary to this. Similarly, for the charging/discharging capacitor, the influence of leakage resistance can be selected on the leakage resistance between the terminals by dividing the capacitor into one for charging and discharging to a high potential and one for charging and discharging to a low potential. Here, the charging/discharging capacitors were also connected in such a way that the influence of leakage resistance was reduced in the same way as the leakage resistance between terminals by dividing the capacitor into one for charging and discharging to a high potential and one for charging and discharging to a low potential. Of course, the 14 high potential terminals and the 13 low potential terminals at this time are DC voltage terminals.

Figure 5a is an equivalent circuit for understanding the effect of Figure 4. In Figure 5a, 17 is the input signal voltage, 1
8 Switches corresponding to diode on and off, 1
9 is a leak resistance, and 20 is a power supply corresponding to the potential difference between the high potential side and the low potential side of adjacent terminals.

Now, while the switch 18 is on, the signal voltage 17 accumulates enough charge in the capacitor, and just before the switch turns off, charges corresponding to the voltages V ₂ and V ₁ are given as initial values. Assuming that, the following formula (3) holds true. Here, a P-function number operator with P=d/dt and 1/P=∫dt is used.

I ₁ R＋I ₃ R＝V _O ……(3) I ₁ R＝I ₂ 1/C _P −V ₂ ……(4) I ₃ R＋I ₄ 1/C _P =V ₁ ……(5) I ₁ +I ₂ + I ₄ = I ₃ ...(6) If we use the inverse transformation with the P function, V=V _O +V ₁ −V ₂ /2・exp(−1/〓〓t)+
V _O /2 [1-exp(-1/CRt)] ...(9) =V _O /2+V ₁ -V ₂ /2exp(-1/CRt)
...(10) Both terminals 1 for the voltage V _P that should be maintained at terminal 12
If 3 and 14 are made to have exactly the same potential difference, then in formula (10),
V ₁ −V ₂ =0, so that the holding voltage V remains V _O /2 and the time constant can theoretically be infinite. Even considering practical element variations, the time constant can be expanded considerably.
Furthermore, even if V _P is not V _O /2, if V _P <V _O is always maintained, the second term of equation (10) means that the time constant can be expanded due to the effect of V ₁ - _{V 2} , which reduces leakage. It is possible to prevent the discharge time constant from decreasing due to current.

If the leakage resistance of the capacitor has a value that does not have much of an effect, capacitor C (3) does not need to be connected to the high potential side and the low potential side, and the equivalent circuit in this case is shown in Figure 5b. Let's be like this.
If Figure 5b is solved in the same way as Figure 5a, the result of equation (17) is obtained, Inverse transformation I ₃ R=V _O /2 (1-exP-2/CORt) +V ₁ exp-2/CORt ...(16) =V _O /2+(V ₁ -V _O /2)exp-2/CORt
...(17) To make C in Figure 5 a equivalent to Figure 5 b, C _O in equation (17) corresponds to C _O = 2C, so it becomes equation (18) V = 1 ₃ R=V _O /2+(V ₁ -V _O /2)exP(-1/C
_R t) ...(18) Since it is simply replaced with V ₂ =V _O /2, the same effect can be obtained.

As described above, in a voltage holding circuit where leakage between terminals cannot be ignored, the terminals adjacent to a given terminal are arranged so that their potentials are opposite to the voltage held by that given terminal, respectively. , and if the design is designed to have the characteristics of a voltage divider so that the holding voltage is at the midpoint of the potential difference, the impedance, which is one constant of the discharge time constant, can be set large, and the impedance, which is the other constant, can be set large. It is possible to select a small capacitor capacity, and it is possible to realize the use of small elements suitable for high density. In addition, in today's high-density environment, not only capacitors but also integrated circuit devices are becoming smaller, and with the advent of packages in which the distance between terminals has been reduced to half of the conventional one, the voltage holding circuit of the present invention has become even more compact. Increase usefulness.

Furthermore, even when miniaturization of the element is not particularly required, it is natural that the ability to obtain the same level of performance with a small-capacity capacitor is highly effective in reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a diagram of a conventional detection circuit, and FIG. 2 shows input and output signal waveforms of the circuit. 3 and 4 are detection circuit diagrams of each embodiment of the present invention, and FIG. 5 is a predicted equivalent circuit diagram of the circuit of the embodiment of the present invention. 1... Signal source, 2... Detection diode, 3...
...Charge/discharge capacitor for voltage holding, 4...Emitter follower transistor for buffer, 5...Emitter resistor, 6...Output terminal, 7...Reference power supply voltage terminal, 8...Reference ground terminal, 9... Signal source side DC bias, 10... Buffer stage circuit, 11... Leak resistance, 12... Capacitor connection terminal, 1
3, 14... Adjacent terminal, 15, 16... Leak resistance between terminals.

Claims (1)

[Claims] 1. A first terminal is provided at a connection point between the holding voltage supply means and the holding voltage input terminal of a high input impedance buffer stage that transmits the holding voltage from the holding voltage supply means, and the first terminal and A voltage holding capacitor is connected between an external terminal having a predetermined potential, and a second capacitor, which is set at a potential higher than the first terminal potential, is connected on both sides of the first terminal at a position close to the first terminal. A voltage holding device comprising a terminal and a third terminal set to a potential lower than the potential of the first terminal. 2 The voltage holding capacitor is divided into a first and a second capacitor, one terminal of each is connected to the first terminal, the other terminal of the first capacitor is connected to the second terminal, and the second 2. The voltage holding device according to claim 1, wherein the other terminal of the capacitor is connected to the third terminal.