JPS615555A - Insulating type semiconductor device - Google Patents
Insulating type semiconductor deviceInfo
- Publication number
- JPS615555A JPS615555A JP59125164A JP12516484A JPS615555A JP S615555 A JPS615555 A JP S615555A JP 59125164 A JP59125164 A JP 59125164A JP 12516484 A JP12516484 A JP 12516484A JP S615555 A JPS615555 A JP S615555A
- Authority
- JP
- Japan
- Prior art keywords
- header
- semiconductor device
- package
- chip
- pieces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕 ゛
本発明は実験時絶縁処置を施すことなく直接実装できる
絶縁型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an insulated semiconductor device that can be directly mounted without performing insulation treatment during experiments.
従来、半導体装置のパッケージング技術として、量産性
に！れたトランスフアレビンモールド（モールド）技術
が多用されている。また、レジンパッケージ型の半導体
装置の一つとして、電子材料。Conventionally, it has been used as a packaging technology for semiconductor devices for mass production! Transfer Levin mold (mold) technology is widely used. Electronic materials are also used as a type of resin packaged semiconductor device.
１９８１年、１１月号、４２〜４６頁における横型半導
体装置が知られている。この絶縁型半導体装置は、従来
のこの種（ＴＯ２２０型）の半導体装置における実装作
業の煩わしさを軽減するべく開発されたものであって実
装時、ヘッダに設けら、れた取付孔に絶縁管を挿入する
手間暇を削減するために取付孔の内周面をレジンで被う
とともに１、−′＞ラダの裏面にマイカ等の絶縁板を介
在させて取付仮に半導体装置を固定する手間暇を削減す
るために、ヘッダの裏面をレジンで被った構造となって
いる。また１、この絶縁型半導体装置におけるへさ
ラダ裏面側のレジン厚かは、所望絶縁破壊電圧を維持す
ることを限度として放熱性を良好とするために、できる
限り薄いことが望ましく、前記文献にも記載されている
ように、その厚さはたとχば、０．３５〜０．４５ｍｍ
程度となっている。さらに、この絶縁型半導体装置は、
ヘッダとレジンとの界面を伝わって侵入する酸化性物質
（水分、酸素等のガス）の侵入を阻止させるために、出
来得る限りのヘッダ部分をレジンで被った構造となって
いる。A horizontal semiconductor device is known, as described in the November issue of 1981, pages 42-46. This insulated semiconductor device was developed to reduce the hassle of mounting work on conventional semiconductor devices of this type (TO220 type). In order to reduce the time and effort required to insert the semiconductor device, the inner circumferential surface of the mounting hole is covered with resin, and an insulating plate such as mica is interposed on the back side of the ladder to reduce the time and effort of temporarily fixing the semiconductor device. In order to reduce the cost, the back side of the header is covered with resin. In addition, 1. It is desirable that the resin thickness on the back side of the hesa ladder in this insulated semiconductor device be as thin as possible in order to maintain good heat dissipation while maintaining the desired dielectric breakdown voltage. As also described, its thickness is, for example, 0.35 to 0.45 mm.
It has become a degree. Furthermore, this insulated semiconductor device
In order to prevent oxidizing substances (gases such as moisture and oxygen) from entering through the interface between the header and the resin, the header is covered with resin as much as possible.
一方、本出願人も同様な絶縁型半導体装置を０充してい
るが、この絶縁型半導体装置はその製が時、すなわち、
パッケージ形成のモールド時、ンッダは裏面をもレジン
で被う必要があるこ、とがｔヘッダはモールド型の一部
で支持さルてモールｌ型の゛キャビティの底から浮き、
この状態でも一ノ１ドが行われる。この結果、前記ヘッ
ダの支持さ才た部分がパッケードから露出してしまい、
高い耐絶縁破壊電圧特性が必要な製品群（耐絶縁破壊電
圧が１５００〜２０００Ｖと高いテレビの水平仰向用ト
ランジスタ等）には、従来のこの種の絶縁型半導体装置
の構造は適用し難いと考えられること、が発明者の検討
め結果よりあきらがとなった。On the other hand, the present applicant has also developed a similar insulated semiconductor device, but this insulated semiconductor device was manufactured at the time of manufacture, that is,
When molding to form a package, the back side of the header must also be covered with resin, but the header is supported by a part of the mold and floats from the bottom of the mold's L-shaped cavity.
Even in this state, a single stroke is performed. As a result, the supported portion of the header is exposed from the package.
It is difficult to apply the conventional structure of this type of insulated semiconductor device to product groups that require high dielectric breakdown voltage characteristics (such as transistors for horizontal and vertical televisions with high dielectric breakdown voltage of 1,500 to 2,000 V). The inventor's research has revealed that it is possible to do so.
本発明の目的は耐絶縁破壊電圧が高い絶縁型半導体装置
を提供することにある。An object of the present invention is to provide an insulated semiconductor device with high dielectric breakdown voltage resistance.
本発明の他の目的は実装設計がし易い絶縁型非導体装置
を提供することにある。Another object of the present invention is to provide an insulated non-conductor device that is easy to design and package.
本発明の前記ならびにそのほがの目的と新規な特徴は、
本明細書の記述および添付図面からあきｇ らかに
なるであろう。The above-mentioned objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.
ｌ 〔発明の概要〕
□ ゛ 本願において開示される発明のうち代表的な
ものの概要を簡単に説明すれば、下記のとおりであζ
る。l [Summary of the invention] □ ゛ A brief overview of typical inventions disclosed in this application is as follows.
Ru.
レ すなわち、本発明の絶縁型半導体装置は、そ
のＬ 製造におけるモールド型のキャビティ底から
八ツ（ダを浮かせる結果化じてしまったパレケージにお
ｔ けるヘッダの露出部分は、絶縁性のレジンで被
わ薔 れていることから、耐絶縁破壊電圧は向上す
る。In other words, in the insulated semiconductor device of the present invention, the exposed portion of the header in the package, which is formed as a result of floating the mold from the bottom of the mold cavity during manufacturing, is made of insulating resin. Since it is covered, the dielectric breakdown voltage is improved.
ｋ また、絶縁型半導体装置はその耐絶縁破壊電圧
が１ 向上することから、その実装時のレイアウト
等が−し易くなり、実装設計の余裕度が向上する。In addition, since the dielectric breakdown voltage of the insulated semiconductor device is improved by 1, the layout etc. at the time of mounting become easier, and the latitude in mounting design is improved.
第１ ［１’は本発明の一実施例による絶縁型半導体装
置の製造状態な示す斜視図、第２図は同じく一部を切り
欠いた状態における絶縁型半導体装置の斜視図である。1 is a perspective view showing a manufacturing state of an insulated semiconductor device according to an embodiment of the present invention, and FIG. 2 is a perspective view of the insulated semiconductor device in a partially cut-away state.
本実施例の絶縁型半導体装置（絶縁型パワートランジス
タ）は、第２図に示されるように、レジンからなるパッ
ケージｌと、このパッケージ１の一端面から突出する３
本のり一部２と、からなっている。また、パッケージ１
にはネジ挿入孔３が設けらＫている６
つぎに、第１図を参照しながら、このトランジスタの製
造方法について説明しながら、トランジスタの細部につ
いて説明する。As shown in FIG. 2, the insulated semiconductor device (insulated power transistor) of this embodiment includes a package l made of resin and a 3
It consists of part 2 of book glue. Also, package 1
A screw insertion hole 3 is provided in the transistor 6.Next, the details of the transistor will be explained while explaining the manufacturing method of this transistor with reference to FIG.
こ゛のトランジスタの組立にあっては、第１図で示すよ
うなリードフレーム４が用いられている。In assembling this transistor, a lead frame 4 as shown in FIG. 1 is used.
このリードフレーム４は放熱性の優れた金属板、たとえ
ば、鉄−ニッケル系合金、銅系合金等の０．１〜０．２
５ｍｍ程度の厚さの薄い金属板をエツチングあるいはプ
レス等によって所望パターンに形成するとともに、プレ
ス成型することによって得られる。すなわち、リードフ
レーム４は細い枠部５と、この枠部５の一側から平行に
延在する３本のリード２を有している。３本のり−ド２
は前記枠部５と平行に延在するーいダム片６によって連
結されている。このダム片６はリードフレーム４の取扱
時には補強部材の役割を果たし、レジンモールド時には
注入されたレジンの流出を防ぐダムの役割を果たす６両
側のリード２の先端部分は両側に僅かに張り出して幅広
となり、ワイヤ接続部７を構成している。ワイヤ接続部
７の張り出しはパッケージ１のレジン部分に張り出し部
分が喰い込んでパッケージ１がらリード２が抜けないよ
うにするためである。This lead frame 4 is made of a metal plate with excellent heat dissipation, such as iron-nickel alloy, copper alloy, etc.
It is obtained by forming a thin metal plate with a thickness of about 5 mm into a desired pattern by etching or pressing, and then press-molding it. That is, the lead frame 4 has a thin frame part 5 and three leads 2 extending in parallel from one side of the frame part 5. 3 rides 2
are connected by a dam piece 6 extending parallel to the frame portion 5. This dam piece 6 plays the role of a reinforcing member when handling the lead frame 4, and plays the role of a dam to prevent the injected resin from flowing out during resin molding 6 The tips of the leads 2 on both sides are wide and slightly overhang on both sides. This constitutes the wire connection section 7. The purpose of the overhang of the wire connection portion 7 is to prevent the overhang from biting into the resin portion of the package 1 and the leads 2 from coming out of the package 1.
一方、中央のり−ド２は下方に一段折れ曲がり、幅広の
ヘッダ８に連結されている。このヘッダ８のリード２と
の連結側はチップ（半導体装置）９を固定するチップ取
付領域１ｏとなっすいる。また、ヘッダ８の他端部分は
その両側から細いアーム１１を有している。このアーム
１１は途中から階段状に一段高く延在し、モールド時の
へラダ８のモールド高さを規定する高さ規定片１２とな
っ □ている。なお、一対のアーム１１間の空間
部分はネジ挿入孔形成用空間１３となっている。On the other hand, the center board 2 is bent downward one step and connected to a wide header 8. The side of the header 8 connected to the leads 2 serves as a chip mounting area 1o in which a chip (semiconductor device) 9 is fixed. Further, the other end portion of the header 8 has thin arms 11 from both sides thereof. This arm 11 extends one step higher from the middle in a step-like manner, and serves as a height regulating piece 12 that defines the mold height of the spatula 8 during molding. Note that the space between the pair of arms 11 serves as a space 13 for forming a screw insertion hole.
このようなリードフレーム４を用いてトランジスタを組
み立てる場合には、同図に示すように、リードフレーム
４のチップ取付領域（チップ固定領域）１０にチップ９
が最初に固定される。つぎに、チップ９の電極と各リー
ド２とはワイヤ１４で接続される。その後、このリード
フレーム４は、特に図示はしないが、モールド型の上型
と下型との間に挟持される。この際、前記高さ規定片１
２は上型と下型に設けられた細い円柱状の突子によって
挟持され、ヘッダ８はモールド型の下型と上型とによっ
て形成されるキャビティの底から浮かぶ。そして、ヘッ
ダ８がキャビティ内で浮かんだ状態でモールドが行われ
、直方体のパッケージ１が形成される。したがって、第
１図に示されるように、パッケージ１の高さ規定片１２
が位置する部分に対応する部分には、細い孔１５が発生
してしまう。この孔１５の底にはへ、ラダ８が繋がる高
さ規定片１２が露出する。When assembling a transistor using such a lead frame 4, as shown in the figure, a chip 9 is placed in the chip mounting area (chip fixing area) 10 of the lead frame 4.
is fixed first. Next, the electrodes of the chip 9 and each lead 2 are connected with wires 14. Thereafter, this lead frame 4 is held between an upper mold and a lower mold, although not particularly shown. At this time, the height regulating piece 1
2 is held between thin cylindrical protrusions provided on the upper and lower molds, and the header 8 floats from the bottom of the cavity formed by the lower and upper molds. Then, molding is performed with the header 8 floating within the cavity, and a rectangular parallelepiped package 1 is formed. Therefore, as shown in FIG.
A thin hole 15 is generated in a portion corresponding to the portion where the . At the bottom of this hole 15, a height regulating piece 12 to which the ladder 8 is connected is exposed.
また、前記モールド時、一対のアーム１１間のキャビテ
ィ部分にはモールド型に設けられた円柱体が位置してい
て、モールド後にはパッケージ１を表裏に渡って貫通す
るネジ挿入孔３が形成される。このネジ挿入孔３はパッ
ケージ１によって形成されている。Further, during the molding, a cylindrical body provided in the mold is located in the cavity between the pair of arms 11, and after molding, a screw insertion hole 3 is formed that passes through the package 1 from the front and back. . This screw insertion hole 3 is formed by the package 1.
つぎに、前記パッケージ１の孔１５はたとえば、エポキ
シレジンの如き１６が注入されて塞がれる（第゛２図参
照）。したがって、ヘッダ８部分は完全にパッケージ１
および絶縁体１６によって被われる。注入方法は、特に
限定されないがボッティング及び塗布作業で行なうこと
により低コスト化が実現できる。Next, the hole 15 of the package 1 is filled with 16, such as epoxy resin, to close it (see FIG. 2). Therefore, header 8 part is completely package 1
and covered by an insulator 16. The injection method is not particularly limited, but cost reduction can be achieved by performing botting and coating operations.
つぎに、リードフレーム４の不用となる部分、すなわち
、枠部５、ダム片６は切断除去され、第２図に示される
ようなトランジスタが製造される。Next, the unnecessary portions of the lead frame 4, ie, the frame portion 5 and the dam piece 6, are cut and removed, and a transistor as shown in FIG. 2 is manufactured.
第２図では、ネジ挿入孔３が絶縁体１６によって塞がれ
た状態を部分的にパッケージ１部分を切り欠くことによ
って示しである。In FIG. 2, the state in which the screw insertion hole 3 is blocked by the insulator 16 is shown by partially cutting out the package 1.
１、本発明の絶縁型のパワートランジスタは、ヘッダ８
の主面および裏面は絶縁性のレジンで被われるとともに
、パワートランジスタのモールド時のヘッダ□８の支持
によって生じてしまうヘッダ８Ｉの一部の露出部分（高
さ規定片１２部分）は、絶縁体１６によって被覆されて
いることから、ヘッダ部分における耐絶縁破壊電圧が向
上するという効果が得られる。1. The isolated power transistor of the present invention has a header 8
The main and back surfaces of the header 8I are covered with an insulating resin, and a part of the exposed part (height-defining piece 12 part) of the header 8I that is caused by the support of the header □8 when molding the power transistor is covered with an insulating resin. 16, the effect of improving dielectric breakdown voltage resistance in the header portion can be obtained.
２、上記１から、本発明のパワートランジスタは耐絶縁
破壊電圧が高くなること、およびリード２を除く部分は
完全にパッケージ１等によって絶縁されていることから
、実装におけるレイアウト設計の余裕度が向上し、実装
設計が容易となるという効果が得られる。2. From 1 above, the power transistor of the present invention has a high dielectric breakdown voltage, and the parts other than the lead 2 are completely insulated by the package 1, etc., so the margin for layout design during mounting is improved. However, the effect of facilitating implementation design can be obtained.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。たとえば、ヘッダの高さ
規定片がモールド後に、パッケージの表面部分で切断さ
れるような構造の絶縁型半導体装置の場合は、露出する
高さ規定片部分を絶縁体で被うことによって、絶縁型半
導体装置の耐絶縁破壊電圧の向上を図ることができる。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the case of an insulated semiconductor device whose structure is such that the height regulating piece of the header is cut off at the surface of the package after molding, the exposed height regulating piece can be covered with an insulator. It is possible to improve the dielectric breakdown voltage of the semiconductor device.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である絶縁型半導体装置の
技術に適用した場合について説明したが、それに限定さ
れるものではなく、たとえば、前記同様の構造をした集
積回路装置の製造技術などに適用できる。The above explanation has mainly been about the case where the invention made by the present inventor is applied to the technology of insulated semiconductor devices, which is the background field of application, but the invention is not limited thereto. It can be applied to manufacturing technology of structured integrated circuit devices.
第１図は本発明の一実施例による絶縁型半導体装置の製
造状態を示す斜視図。
第２図は同じく一部を切り欠いた状態における絶縁型半
導体装置の斜視図である。
１・・・パッケージ、２・・・リード、３・・・ネジ挿
入孔、４・・・リードフレーム、５・・・枠部、６・・
・ダム片、７・・・ワイヤ接続部、８・・・ヘッダ、９
・・・チップ（半導体素子）、１０・・・チップ取付領
域、１１・・・アーム、１２・・・高さ規定片、１３・
・・ネジ挿入孔形成用空間、１４・・・ワイヤ、１５・
・・孔、１６・・・絶縁体（レジン）。FIG. 1 is a perspective view showing a manufacturing state of an insulated semiconductor device according to an embodiment of the present invention. FIG. 2 is a perspective view of the insulated semiconductor device with a portion cut away. DESCRIPTION OF SYMBOLS 1... Package, 2... Lead, 3... Screw insertion hole, 4... Lead frame, 5... Frame, 6...
・Dam piece, 7...Wire connection part, 8...Header, 9
... Chip (semiconductor element), 10... Chip mounting area, 11... Arm, 12... Height regulation piece, 13.
...Screw insertion hole formation space, 14...Wire, 15.
... Hole, 16... Insulator (resin).
Claims (1)
ヘッダを浮かせてモールドが行われる絶縁型半導体装置
であって、前記モールドによって生じたヘッダの露出部
分は絶縁体で被われてなることを特徴とする絶縁型半導
体装置。1. An insulated semiconductor device in which molding is performed with the header floating from the bottom of a mold cavity during package formation, characterized in that the exposed portion of the header caused by the molding is covered with an insulator. Insulated semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59125164A JPS615555A (en) | 1984-06-20 | 1984-06-20 | Insulating type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59125164A JPS615555A (en) | 1984-06-20 | 1984-06-20 | Insulating type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS615555A true JPS615555A (en) | 1986-01-11 |
Family
ID=14903461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59125164A Pending JPS615555A (en) | 1984-06-20 | 1984-06-20 | Insulating type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS615555A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04136484A (en) * | 1990-09-28 | 1992-05-11 | Matsushita Electric Ind Co Ltd | Electronic ignitor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5917273A (en) * | 1982-07-20 | 1984-01-28 | Nec Corp | Resin sealed semiconductor device |
-
1984
- 1984-06-20 JP JP59125164A patent/JPS615555A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5917273A (en) * | 1982-07-20 | 1984-01-28 | Nec Corp | Resin sealed semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04136484A (en) * | 1990-09-28 | 1992-05-11 | Matsushita Electric Ind Co Ltd | Electronic ignitor |
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