JPS6155067B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a terminal testing device for a component having a plurality of terminals, such as a writable read-only memory. It is an object of the present invention to provide a terminal testing device that can determine whether there is continuity between terminals.

For example, when writing various programs to writable read-only memory, a predetermined address signal is applied to the address input terminal, a write current corresponding to the data to be written to that address is applied to the data terminal, and the write current Predetermined data is stored by selectively fusing, for example, a fusing portion in an integrated circuit, or by semi-permanently charging a gate insulating layer of a field effect transistor formed as a memory element. . When writing, for example, even if the address input terminal or data terminal is controlled to electrically disconnect the terminal and the internal circuit by an inhibit signal, there is a risk of accidentally touching a common potential point inside or outside the integrated circuit. If the terminals are connected to each other, or the terminals are electrically connected to each other, there is a drawback that data may be stored at an address different from the address to be written, or an erroneous program may be stored.

In particular, when writing the same program to multiple read-only memories at the same time using one writing device, the address input terminals and data terminals of each read-only memory are commonly connected to each other, and each of the commonly connected An address signal and a write current or voltage are applied to an address input terminal and a data terminal so that writing is simultaneously performed in a plurality of read-only memories. In such a case, if the terminals of even one of the multiple read-only memories are short-circuited to a common potential point, or if the terminals are electrically connected, erroneous writing may occur to all read-only memories. However, at the same time, a large amount of read-only memory becomes defective, resulting in a major inconvenience.

As another example, even in parts with multiple terminals, such as cathode ray tube sockets, printed circuit board connectors, or printed circuit boards, each terminal must be insulated and held separately.
If short-circuits are accidentally caused internally, if this is incorporated into a device, there is a risk that the device will malfunction, or worse, an accident may occur that may damage other parts.

For this reason, a method of testing the condition of each terminal of a component having a plurality of terminals one by one using a continuity tester may be considered, but this requires time and labor and cannot be processed in large quantities in a short period of time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a terminal testing device that can test the condition of a large number of terminals of a component having a plurality of terminals in a short period of time.

The present invention provides a means for simultaneously applying a potential of the same logic to all terminals to be inspected, determining their logical state, and determining whether or not any one of them is short-circuited to a common potential point. means for sequentially applying a potential of a logic different from that of the other terminals to one of the terminals to determine whether or not the potential is output to the other terminals, and using these determining means to determine the state of the terminal. This is what we are trying to test.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. This example shows a case where the device according to the present invention is incorporated into a read-only memory writing device. In the figure, 1 indicates the test object, that is, a read-only memory in which various programs are to be written from now on, and shows a case where the same program is written to multiple read-only memories 1a, 1b, 1c, etc. at the same time. . For this purpose, each read-only memory 1a, 1
The address input terminals and data terminals of the terminals b, 1c, . It goes without saying that the read-only memories 1a, 1b, 1c... are connected via sockets, and the read-only memories 1a, 1c...
b, 1c... are assumed to be detachable from the test board. In addition, each read-only memory 1
It is assumed that a control signal is applied to the inhibit terminals of a, 1b, 1c, .

Reference numeral 3 indicates a terminal testing device according to the present invention, and 4 indicates a group of gate circuits that can disconnect the connection between the terminal testing device 3 and the writing device 2 as necessary.
In other words, this gate circuit group 4 instantaneously turns on the operation start command switch 5 of the terminal test device 3 to start the test device 3, and at the same time operates the flip-flop 6.
is controlled to be closed by the output of , and operates to disconnect the writing device 2 and the test object 1 .

It is assumed that the flip-flop 6 is held in a reset state in the initial state, and is reset by turning on the switch 5, and the output of the output terminal falls to, for example, L logic, and the gate circuit group 4 is closed by the L logic signal. controlled. On the other hand, the output terminal Q of the flip-flop 6 is inverted to H logic, and this H logic signal turns on each switch element of the switch element group 7, thereby electrically connecting the terminal testing device 3 and the object under test 1. A pull-up resistor group 8 is connected to the device 3 side of each switch element in the switch element group 7, and a potential of the same logic is simultaneously applied to each terminal of the device under test 1, and each terminal of the device under test 1 is sequentially connected to the other terminals. A shift register 9 constituting means for applying a potential of a different logic to the terminal is connected.

All output terminals Q _a to Q _d of shift register 9 are L.
In the initial state of logic, a potential of H logic is applied to each terminal of the test object 1 through the switch group 7 from a plurality of pull-up resistors R. It is determined whether or not the given H logic potential is held, thereby determining whether or not the terminal of the test object 1 is electrically connected to the common potential point.

10 shows this judgment circuit. The determination circuit 10 includes, for example, a plurality of exclusive OR circuits 11a, 11b, 1
1c..., a NAND gate 12, and a flip-flop 13. One input terminal of each of the exclusive OR circuits 11a, 11b, 11c... is connected to the connection point between the pull-up resistor R and the switch element group 7, and the other input terminal is connected to each output terminal _Qa , Connect to Q _b , Q _c …. Exclusive OR circuits 11a, 11b, 11c
. . are commonly connected and connected to one input terminal of the NAND gate 12 via an inverter 14 as necessary. The output of the output terminal Q of the flip-flop 6 is applied to another input terminal of the NAND gate 12, and a timing signal for determination is applied from the timing signal generator 16 to another input terminal. Output terminals Q _a , Q _b , Q _c . . . of means 9
In the initial state, for example, all output logic L as described later. Therefore, if all the terminals of the test object 1 are not connected to the common potential, H logic is applied to one input terminal of all the exclusive OR circuits 11a, 11b, 11c, etc., and H logic is applied to the other input terminal. is given L logic. Therefore, all outputs of the exclusive OR circuits 11a, 11b, 11c, . . . become H logic, and the output of the inverter 14 becomes L logic. Therefore, even if a timing signal of H logic is applied from the timing signal generator 16 to one input terminal of the NAND gate 12, the output of the NAND gate 12 continues to output the H logic, and the flip-flop 13 is not set. The output terminal Q of is held at L logic, and the light emitting diode constituting the good/defective indicator 15 does not light up. In other words, it can be seen that each terminal of the test object 1 is not electrically connected to the common potential.

If any one of the terminals of the test object 1 is electrically connected to the common potential, one end of the pull-up resistor R connected to that terminal becomes L logic. Therefore, that L
The exclusive OR circuit connected to the pull-up resistor R which has become logic outputs L logic. For this reason, the output of the inverter 14 outputs H logic, so when an H logic timing signal is given from the timing signal generator 16 to one input terminal of the NAND gate 12, all inputs of the NAND gate 12 become H logic and a timing signal is given. The NAND gate 12 outputs L logic only while the signal is being held. As a result, the flip-flop 13 is set by the fall of the signal and outputs an H logic signal from the output terminal Q, so that the display 15 lights up and remains lit. Therefore, it is displayed that the test object 1 has a defective terminal.

On the other hand, the clock input terminal CK of shift register 9
A pulse is given from the timing signal generator 16 to output terminals Q _a , Q _b , Q
_c ... sequentially outputs H logic. In other words, the timing signal generator 16 receives a clock pulse P a having a frequency of, for example, about 1 MHz from a clock pulse source 17 _.
(Fig. 2A) is generated. This clock pulse P _a is applied to the clock input terminal CK of the shift register 19 through a gate 18 whose opening and closing are controlled by the output of the output terminal Q of the flip-flop 6. This shift register 19 has 4-bit output terminals Q _a , Q _b , Q _c , and _d in this example, and outputs from all output terminals Q _a to Q _d are applied to the input of a NAND gate 20 . The output of the NAND gate 20 is supplied to the signal input terminal SIN. Therefore, if the outputs of the respective output terminals Q _a to Q _d of the shift register 19 are all at L logic in the initial state, the NAND gate 20
The output becomes H logic. Clock input terminal
When one clock pulse P _a is input to CK, H logic is output to the output terminal Q _a . Output terminal Q _a is H
When the logic is output, the output of the NAND gate 20 is inverted to L logic. Therefore, when the second clock pulse is applied to the input terminal CK, the output of the output terminal Q _a is inverted to L logic, and the output terminal Q _b becomes H logic. In this way, the output terminals Q _a to Q _d sequentially output H logic as shown in FIGS. 2B to 2E.

The output of the output terminal Q _d of the shift register 19 is applied to the shift register 9 . H logic is applied to the signal input terminal SIN of the shift register 9 from the output terminal Q of the flip-flop 21 from the time of startup. Therefore, shift register 9 and shift register 1
When the first pulse is applied from output terminal Q _d of No. 9, output terminal Q _a outputs H logic. The flip-flop 21 is reset by this H logic output, and each time a pulse is output from the output terminal Q _d of the shift register 19, the output terminals Q _a , Q _b , Q _c . . . of the shift register 9 are reset as shown in FIG. , G, and H, the H logic is sequentially output. Therefore, each time H logic is sequentially output from the output terminals Q _a , Q _b , Q _c .
Logic is given. Therefore, if a terminal to which L logic is applied and another terminal to which H logic is applied are electrically connected, that terminal should be H logic, but becomes L.
It becomes logical. Therefore, L logic is input to both input terminals of the exclusive OR circuit connected to the conducting terminal, and therefore, the output of the exclusive OR circuit becomes L logic. On the other hand, the logic of a normal terminal that is not electrically connected to the terminal to which L logic is applied from the shift register 9 through the inverter group 22 is that H logic is applied to it through the pull-up resistor R, so look at the logic of the normal terminal. Both inputs of the exclusive OR circuit shown in FIG. Since both are L logic, these exclusive OR circuits output H logic in any case. Therefore, if all terminals are not electrically connected to any terminal, the output terminals Q _a , Q _b , Q _c . . . of the shift register 9
all exclusive OR circuits 11a, 11b, 11c, . . . continue to output H logic while outputting H logic sequentially. Therefore, during that time, the output of the inverter 14 is L.
Since the output of the NAND gate 13 is held at logic level and continues to output logic H even if the timing signal is supplied, the flip-flop 13 is not inverted and the display 15 does not light up. On the other hand, when the terminals are electrically conductive, the output of the exclusive OR circuit that monitors the logic of the electrically conductive terminals outputs L logic, which causes the flip-flop 13 to be inverted to the set state. The display 15 then lights up. The flip-flop 13 is reset by turning on the start switch 5 during the next test, and at that time the display 1
5 goes out.

In this way, according to the present invention, immediately after turning on the start switch 5, it is first tested whether each terminal of the test object 1 is connected to a common potential point, and then each terminal is electrically connected to each other. If there is a defective terminal in any of the tests, the indicator 15 lights up to indicate that there is a defective product in the test object 1. Therefore, the state of each terminal of the plurality of read-only memories 1a, 1b, 1c... is tested,
If a defective determination is displayed on the display 15, remove the read-only memories 1a, 1b, 1c, . . . one by one from the circuit, operate the switch 5 each time, and check the determination results. It is possible to identify which read-only memory is defective. Therefore, by removing defective products and writing to read-only memories, correct programs can be written to all read-only memories. Therefore, it is possible to prevent a plurality of read-only memories from becoming defective products due to a terminal failure in one read-only memory, and this has a large economical effect. Furthermore, since the time required for one test is several tens of microseconds at most, a large number of parts can be tested in a short period of time.

In the above description, a read-only memory was particularly exemplified as the test object 1, but as explained earlier, the present invention is applicable to, for example, a socket or a socket for a printed circuit board, or even a printed circuit board having multiple terminals. The condition of component terminals can be tested. Also, among semiconductor integrated circuit devices, we tested devices that can maintain the connection between the terminal and the internal circuit in a disconnected state using electrical control signals, such as the terminals of random access memory in addition to the already explained read-only memory. It can also be used to test open collector type semiconductor integrated circuit devices, and its applications are wide-ranging.

Furthermore, in the above, one display 15 is used to determine and display whether each terminal is in contact with a common potential, and to determine and display whether each terminal is mutually conductive. However, it is also possible to use separate indicators to indicate that each terminal is in contact with a common potential and whether or not the terminals are electrically connected to each other. By separating the indicators in this way, it is possible to determine which of the test objects 1 is defective based on the display.

Further, the means 9 for simultaneously applying a potential of the same logic to each terminal of the test object 1 and sequentially applying a potential of a different logic to other terminals in sequence is not limited to the embodiment shown in FIG. 1, but various other methods may be used. For example, as shown in FIG. 3, the polarity of the output of the shift register 9 is first inverted individually by the inverter group 22,
It is also possible to configure the buffer amplifier group 23 to output an H logic potential to each terminal of the polarity inverted output. By using the buffer amplifier in this manner, H logic and L logic can be applied to each terminal without using any particular pull-up resistor.
Therefore, in this case, the shift register 9 serves both as a means for simultaneously applying a potential of the same logic to each terminal, and as a means for sequentially applying a logic different from that to other terminals to each terminal.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIG. 3 is a connection diagram showing another embodiment of the main part of the invention. DESCRIPTION OF SYMBOLS 1...Device under test, 9...Means for simultaneously applying a potential of the same logic to each terminal of the device under test and sequentially applying a potential of a different logic to each terminal, 10...Determination circuit, 15...Display device.

Claims (1)

[Claims] 1 Simultaneously applying a potential of the same logic to each terminal of a component having multiple terminals that are electrically insulated from each other in the initial state, and supplying a clock pulse to one of the terminals of the component with a logic different from that of the other terminals. A shift register that sequentially switches the potential of At the same time, when a potential with a logic different from that of the other terminals is applied to one of the above-mentioned terminals, there is a judgment circuit that judges whether the potential of that logic is output to the other terminals, and this judgment circuit detects a defect. A terminal testing device for components having multiple terminals, which is equipped with an indicator that indicates a defect when detected.