JPS6153875A - Heat sensitizing recording device - Google Patents

Abstract

PURPOSE:To miniaturize a device and to improve its performance by dividing a picture signal of one line to a small area including a prescribed number of a black picture element and driving and recording a heating unit each time the picture signal is supplied to a driving circuit. CONSTITUTION:When a clear signal AS reaches simultaneously when a picture signal is received, a gate 23a of a gate circuit 23 conducts, and in this condition, when a picture signal BS is inputted, a shift input is executed in the order from a leading picture element. When a black picture element number of a shift- inputted picture signal BS becomes a prescribed value, a gate 23b conducts. Therefore, the picture signal led to a shift register 5 is led to a line memory 21 and shift-inputted. Since an output of the gate 23a to the shift register 5 is an L level, after that a signal equivalent to a white picture element is inputted. When the picture signal for one line is inputted to the register 5, a counted-number output ES is generated from a counter 28 and the picture signal for one line can be recorded.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to improvements in thermal recording devices.

[Technical background of the invention and its problems]

Conventionally, as one type of thermal recording device, for example, as shown in FIG. 1, a large number of heating resistors 11 are arranged in a row. ~． I
There is a system in which one line of thermosensitive recording is performed by dividing n into blocks of a predetermined number, connecting the blocks in a matrix, and driving the blocks in a time division manner while switching between the blocks. This device has each heating resistor 11. ~． This has the advantage of simplifying the configuration by reducing the number of wires between the In and the drive circuit 2 and shift register 3, but on the other hand, since it is time-divisionally driven for each block, it is possible to increase the recording speed. The drawback is that it is difficult.

On the other hand, as another conventional heat-sensitive recording device, for example, as shown in FIG. 2, a heating resistor 11. ~． A drive circuit 4 having the same number of drive elements as In is provided, and each time an image signal for one line is input to the shift register 5, this image signal is supplied to the drive circuit 4 via the latch circuit 6. 1
Line heating resistor 11. ~． There is one in which I and N are driven simultaneously. With this device, all heating resistors 1. ~． Since the recording speed can be driven simultaneously, the recording speed can be greatly increased compared to the apparatus shown in FIG.

However, the above device uses all heating resistors 1. ~．
In order to drive n at the same time, it is necessary to provide a very large capacity power supply circuit. For example, if the output voltage of the power supply circuit is 12
If the resistance value of the v1 resistor is 3600, the current flowing through one resistor is approximately 30 mA, and one line is 1728 mA.
The entire thermal head made up of elements (compatible with A4 size) reaches approximately 5OA. Providing a power supply circuit capable of obtaining this current value is very undesirable as it increases the size of the device and increases its cost, and is difficult to implement in, for example, a facsimile device.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a heat-sensitive recording device that can perform high-speed printing without increasing the capacity of a power supply circuit, thereby achieving miniaturization and improved performance of the device.

[Summary of the invention]

In order to achieve the above object, the present invention provides a thermal recording device that supplies an image signal for each line to a drive circuit to simultaneously drive each heating resistor, in which an image signal for one line is supplied to the drive circuit. At this time, by counting the black pixels of the image signal, one line of the image signal is divided into small areas containing a predetermined number of black pixels, and the image signal is supplied to the drive circuit for each of these small areas, and the image signal is White pixels are inserted into the area and supplied to a drive circuit to perform recording.

[Embodiments of the invention]

FIG. 3 shows a circuit configuration of a thermal recording apparatus according to an embodiment of the present invention, and the apparatus is composed of a thermal head 10 and a recording control section 20. The thermal head 10 has 1
A plurality of heating resistors 11 arranged in a row. ~． In and these resistors 11. ~． A drive circuit 3 having the same number of drive elements as In, a shift register 5 for serial-to-parallel conversion of one line's worth of image signals, and a latch circuit 6 that latches the output of this shift register 5 and supplies it to the drive circuit 3. It consists of In other words, the configuration is such that image signals for one line can be recorded simultaneously.

Now, the recording control section 20 selectively selects between the line memory 2 which can store an image signal for one line, the image signal BS supplied from a demodulation circuit (not shown), and the image signal output from the line memory 21. a first dart circuit 22 that selectively outputs the image signal C8 to the first dart circuit 22; and a second dart circuit that selectively supplies the image signal C8 output from the first dart circuit 22 to the shift register 5 of the thermal head 10 or the line memory 21 It is composed of a dart circuit 23, a first control circuit 24 for controlling the second dirt circuit 23, and a second control circuit 25.

The first control circuit 24 consists of a counter 26 and a flip-flop 27, and the counter 26 counts the number of black pixels of both signals CS supplied from the second dart circuit 23 to the shift register 5. A detection signal is is generated every time a predetermined value is reached. Then, the flip-flop 27 is reset by this detection signal IS, and a dirt switching signal JS is generated from this FRI, f floor Z2F, and this y-to switching signal JS causes each of the second dart circuits 23)r''-
The ports 23* and 23b are made conductive reciprocally.

The second control circuit 25 includes a counter 28, two flip-flops 29, 30, and two OR circuits 31, 32.
It is composed of. The counter 28 receives a clear signal A
s is supplied, the counting operation is started, and every time the clock cp for one line of the image signal is counted, the first counting output Es is generated, and the counting operation is continued for a predetermined period from the time when the first counting output ES is generated. A second count output FS is generated each time the count elapses. Then, the first counting output ES is supplied as a latch signal to the latch circuit 6 of the heat sensitive device 10,
The output of the shift register 5 is latched.

Furthermore, the flip-flop 29 is reset by the clear signal As or the printing end signal KS issued from the AND circuit 33, and is also reset by the first counting output ES generated first after this reset. The first gate circuit 22 is dart-controlled by the set output GS. Further, the flip-flop 3o is reset by the first count output ES or clear output As, and is reset by the second count output FS. The set output H8 is then supplied to the drive circuit 4 of the thermal head 10 as a print permission signal.

Next, the operation of the apparatus constructed as above will be explained using FIG. 4. When the clear signal As arrives at the same time as the image signal is received, the flip-flop 2 of the second control circuit 25
9 is reset and the first dart circuit 22's 5''-to 2
2m is not in a conductive state, and the 7-lip float 27 of the first control circuit 24 is set and the second dirt circuit 23
The gate 23a becomes conductive. Therefore, when the image signal BS is input in this state, the image signal BS is directly guided to the shift register 5 of the thermal head 1o, and is shifted and input in order from the first pixel.

Now, in this state, when the number of black pixels of the above-mentioned shift-input image signal BS reaches a predetermined value, for example, 64 pixels, the detection signal S is outputted from the counter 26 and the flip-flop 2
7 is reset, and as a result, the gate 23b of the second dart circuit 23 becomes conductive.

Therefore, the image signal guided to the shift register 5 is
Figure P! After that, the subsequent image signals are led to the line memory 21 and shifted into the line memory 21. Also, at this time, the gate 23 is connected to the shift register 5.
Since the output of a is at the "L" level, a signal corresponding to a white pixel is shifted in following P.

Then, when the image signal for one line is input to the shift register 5 and the first count output E8 is generated from the counter 28 of the second control circuit 25, the latch circuit 6 inputs the image signal of the shift register 5. Since the signal is latched and the flip-flop 3° is reset, the drive circuit 4 is driven, and as a result, one line of image signals input to the shift register 5 is recorded. At this time, since the image signal for one line includes only 64 black pixels, the capacity of the driving power supply circuit is sufficient to simultaneously drive the heating resistors for the 64 pixels. That's fine.

Note that recording of the image signal is performed from the time when the second counting output FS is generated from the counter 28 until the flip-flop 30 is set.

On the other hand, since the flip-flop 27 is set by the generation of the first count output gs, the dart 23h of the second dart circuit returns to the conductive state, and the flip-flop 29 is set, so that the first The dart circuit 22 of
-) 22b becomes conductive. For this reason, the image signal stored in the line memory 21 is supplied to the shift register 5, and is shifted into the shift register 5. At this time, the line memory 2 stores white pixels corresponding to the PL, so the 21 white pixels are first input to the shift register 5, and then the image signal CS is input. It will be done. Therefore, the position of the image signal C8 within one line does not change.

Then, the image signal cS is input to the shift register 5, and when the number of black pixels of the input image signal cs reaches a predetermined value (64 pixels), the first control circuit 24 causes the second The f-to-23b of the dirt circuit 23 is switched to a conductive state.

As a result, the input of the image signal C8 to the shift register 5 is P
2, and subsequent image signals C8 are input to the line memory 21. Also at this time, shift register 5
As in the case of P1, white pixels are input to until the shift register 5 overflows. Therefore, in this case as well, the number of black pixels input to the shift register 5 is P
There are only 64 pixels included in 2.

Then, when the image signal for one line is input to the shift register 5, the first count output F, S is generated from the counter 28, and as a result, the image signal of the shift register 5 is latched by the latch circuit 6. The data is then supplied to the drive circuit 4, where one line is simultaneously recorded. Therefore, in this case as well, only the heating resistors for 64 pixels are driven.

Thereafter, similarly, the image signal CS input to the shift register 5
The input is aborted every time the number of black pixels reaches 64 pixels,
One line is recorded in the remaining area with white pixels inserted.

P3 and p4 in FIG. 4 indicate areas of image signals recorded at that time.

While repeating the above operation, if the first counting output ES is output from the counter 28 before the number of black pixels of the image signal supplied to the shift register 5 reaches 64 pixels, the logical A print end signal KS is generated from the circuit 33. As a result, flip-flop 29 is reset and the circuit returns to its initial state. Note that the image signal input to the shift register 5 at this time (Fig. 4 Pli)
are subjected to recording in the same manner as in the case of PH, . . . +P4.

Thus, recording of the first line image signal is completed. Further, the second line image signal is read out from a buffer circuit (not shown) upon generation of the printing end signal KS, and is a pixel signal containing 64 black pixels as in the case of the first line image signal. It is divided into sections and recorded separately. P6 to P in FIG. 4 indicate image signals recorded at that time.

In this way, in this embodiment, one line of image signal is
Since each signal including four black pixels is divided and recorded for each divided signal, the capacity of the power supply circuit is relatively small enough to simultaneously drive the heating resistor equivalent to 64 pixels. 9. As a result, the conventional (
Compared to the device shown in FIG. 2), the capacity of the power supply circuit can be significantly reduced. In addition, in each divided recording, except for the last recording, recording is performed in each area including 64 black pixels, so recording is always performed in a state where the power capacity that can be used for one recording is fully used. be able to. Therefore, compared to the conventional device (Fig. 1), which records in each preset block regardless of the number of black pixels, it is possible to improve the recording efficiency, thereby shortening the recording time and recording. Speed can be improved.

Next, another embodiment of the present invention will be described with reference to FIGS. 5 and 6. In FIG. 5, the thermal recording apparatus of this embodiment includes a central control circuit (CPU) 50 consisting of a microprocessor as a recording control unit, and a read-only memory (ROM) containing a control program for this CPU.
51, a random access memory (RAM) 52 for writing the image signal BS, and the CPU 50
An input/output circuit (Ilo
) 53, and the recording control operation is performed by the control operation of the CPU 50.

In the figure, DB represents a data bus, AB represents an address bus, and CC represents a control signal line.

FIG. 6 shows a control program for the CPU SO, and the recording control operation of this apparatus will be explained below in accordance with this program. The CPU 50 has a line counter that counts the length of l lines, a black pixel counter that counts black pixels, and a print timer that determines the printing period, and at the same time as starting the operation, first clears the counters and timers. . In other words, perform an initial reset.

When a start signal arrives in this state, first the line counter is started and the address of the RAM 52 is
Then, the first pixel of the image signal is fetched from a buffer circuit (not shown) and stored in the RAM 52.

Then, it is determined whether this first pixel is a black pixel or not, and if it is not black, it is left as is; if it is black, the black pixel counter is incremented by one, and the contents of this black pixel counter are It is determined whether a predetermined value (64) has been reached. In this case, the content of the black pixel counter is still 64.
Since the number of pixels is less than 1, the CPU 50 subsequently determines whether the contents of the line counter have reached the number of pixels for one line (1728), counts up the RAM address by one, and then Capture pixels. Thereafter, as in the case of the first pixel, after performing black pixel determination, etc., the third pixel is captured, and the above-described determination operations are repeated every time a pixel is captured thereafter.

Now, when the content of the black pixel counter reaches 64 during the above operation, the CPU 50 first clears the black pixel counter,
Thereafter, the RAM address is stored in register A, and register A is counted up by one. Next, it is determined whether the line counter value has reached 1728, and if it has not reached 1728, the RAM address is counted up by one, and then the image signal is taken in again, and the above series of black pixel judgments are repeated. . Then, each time the value of the black pixel counter reaches 64, the RAM address at that time is stored in registers B, C, . . .

Then, when the black pixel judgment for one line of image signals is completed and the content of the 9th line counter reaches 1728, the CPU 50 clears and starts the line counter, and then sets the RAM address to O. and then starts reading out the image signal. The contents of the line counter are first compared with the contents of register A, and each pixel of the image signal is read out until the two become equal. When the content of the register A is reached, white pixels are continuously output until the content of the line counter reaches 1728. At this time, the image signal and the white pixel are sequentially sent to the shift register 5 of the thermal head 10 via the Ilo 53. Then, when the pixels for one line are sent to the shift register 5, the CPU 50 clears the line counter, issues a latch output, causes the latch circuit 6 of the thermal head 10 to perform a latch operation, and then drives the A print signal is issued to circuit 4 to start the print timer.

In this way, recording is performed based on each pixel for one line. When this recording is completed, white pixels are output until the value of the line counter reaches the value of register A, and then register B is selected, and from then on until the contents of the line counter match the contents of register B. RAM 5
The image signal is output from 2. When the output of this image signal is finished, white pixels are outputted until the line counter reaches 1728, and when this is finished, the thermal head is driven in the same way as the first recording, and the second line recording is started. have them do it.

Similarly, image signals are outputted according to the values of the RAM addresses specified by registers C, D, ..., X, and white pixels are output to areas other than this image signal, each corresponding to one line. Constructs image signals and performs recording. Then, when the register X that has stored the RAM address of the last pixel of one line is selected, it is determined that recording of all one line has been completed, and the operation shifts to recording the image signal of the second line.

With such a configuration, it is possible to divide one line of image signals into small areas each including 64 black pixels and perform recording for each of these small areas, just as in the first embodiment.

Therefore, the capacity of the power supply circuit only needs to be large enough to simultaneously drive heating resistors corresponding to 64 pixels, and the power supply circuit can be made smaller and the device can be made smaller and lower in price. Further, it is possible to increase the recording speed.

Note that the present invention is not limited to the above embodiments.

For example, the count number of black pixels may be set to a value other than 64, and may be set depending on the capacity of the power supply circuit. In addition, the structure of the thermal head, the structure of the recording control section, etc. can be modified in various ways without departing from the gist of the present invention.

〔Effect of the invention〕

As described in detail above, the present invention divides one line of image signals into small areas each including a predetermined number of black pixels by counting the black pixels of one line of image signals, and divides these small areas into 91,947 minutes of recording signals are made up of the image signal and the white image line inserted to fill in the other areas, and each time these recording signals are supplied to the drive circuit, the heating resistor is driven. In particular, one line of image signals is recorded.

Therefore, according to the present invention, it is possible to provide a thermal recording device that can perform high-speed printing without increasing the capacity of the power supply circuit, and that can reduce the size of the device and improve its performance.

[Brief explanation of the drawing]

1 and 2 are schematic diagrams of a conventional thermal recording device, FIG. 3 is a circuit diagram of a thermal recording device according to an embodiment of the present invention, and FIG. 4 is used to explain the operation of the device. FIG. 5 is a circuit diagram of a thermal recording device according to another embodiment of the present invention, and FIG. 6 is a flowchart showing control details of the device. 1, ~. n...Heating resistor, 4...Drive circuit, 5.
...Shift register, 1o...Thermal head, 2°...
- Recording control unit, 21... line memory, 22... first dirt circuit, 23... second dirt circuit, 24...
...First control circuit, 25...Second control circuit, 26
．． 28...Kanuta, 27,29.30...Flip-flop, 5o...CPU151...ROM.

Claims (1)

[Claims] In a thermal recording device that simultaneously drives a group of heating resistors by supplying an image signal for each line to a drive circuit, the black pixels of the image signal for each line are counted for each line of the image signal. means for dividing an image signal into a plurality of areas each including a predetermined number of black pixels, and recording signals for one line each by means of the divided image signals for each of these areas and white pixels inserted into other areas. 1. A thermal recording apparatus comprising means for recording one line by supplying each of these recording signals to the drive circuit and driving a group of heating resistors.