JPS6153764A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent drop of resistance value of a high resistance poly-Si by ohmic-connection between a high resistance poly-Si and a low resistane poly-Si in both sides of a high melting point metal. CONSTITUTION:A high melting point metal is deposited only to the area where Si is exposed within a buried contact hole of a high resistance poly-Si 12 and a low resistance poly-Si 11 and a high melting point metal 31 such as tungsten is selectively buried thereto. The ohmic-connection of poly-Si 11 and poly-Si 12 in both sides of a high melting point metal 31 can eliminate existing disadvantage that high concentration impurity in the poly-Si 11 is diffused into the poly-Si 12 and thereby an effective high resistance length Lo of poly-Si 12 is reduced. Therefore, drop of a low resistance value of poly-Si 12 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device including a polycrystalline silicon (polysilicon) high resistance element.

[Technical background of the invention and its problems]

In the semiconductor MOS static memory field, this is an E/R type smestatic memory self-flip flow that uses a high-resistance polysilicon layer as a load element.

The memory cell consists of a memory cell block circuit, four transistors forming an access gate to a memory cell, and a high resistance load element connected to a pair of storage nodes. By the way, conventionally, in order to increase the integration density of memory cells, a first polysilicon layer of low resistance and a second polysilicon layer of high resistance (the high resistance load element) are used.
Direct buried contact hole (BuriedCo)
ntact Hole).

FIG. 3 shows a circuit diagram of a high resistance load type static memory cell, FIG. 4 shows a flat turn plan view thereof, and FIG. 5 shows a cross-sectional structural diagram taken along the line V--V in FIG. 4. In Figure 3, 1
, 2 are transistors forming a flip-flop, 3,
4 is a transistor constituting an access gate, 5 and 6 are high resistance load elements, VCCIVBB is a power supply, B is a bit line, and W is a word line. In Fig. 4, 1 is the low resistance first point, t? The IJ silicon layer 12 is a high resistance second rI! 13 is a buried contact hole in the first and second polysilicon layer, 14 is a pit line made of aluminum, 15 is an N+ diffusion layer, and 16 is a low resistance impurity diffusion region into the second polysilicon layer. (vcc line)
It is. In FIG. 5, 2 is an N type substrate, 22 is a P well layer, 23 is an r-to-Sin film, and 24 is a field 5i.
02 film, 25°26 is a 5i02 film, and 27 is a nocination film.

The power supply VCC line 16 in the memory cell is made of low-resistance polycrystalline silicon by doping and diffusing impurities into second polysilicon. The first polysilicon layer 1 including the word line contains impurities to lower the resistance.

However, as shown in FIG. 5, the second f? The impurity in the low resistance portion 16 of the IJ silicon diffuses into the second polysilicon at a certain speed, and eventually spreads to a distance L1 of usually several microns. The other end of the high-resistance polycrystalline silicon layer 12 is connected to the first polysilicon fijl of the storage node in the cell.
Since it is contact-connected to l via a buried contact,
Here again, impurities diffuse from the first polysilicon layer 11 into the second polysilicon layer 12 to a distance of several μm, and the resistance is sufficiently low because the first polysilicon layer 11 is used as a word line. Therefore, it is extremely difficult to keep the impurity diffusion distance into the second polysilicon 12 through the buried contact 13 small. The only way to suppress the impurity diffusion distance is to reduce the subsequent heat treatment temperature, heat treatment time, etc. to a low temperature and short time, but cryogenic processing is a major challenge for ultra-LSI. Therefore, there is an effective high resistance length on the second polysilicon film 12. is narrowed by the length "Ip Lt" due to impurity diffusion from both ends.

In recent years, the demand for high integration of static memories has been increasing, as is the case with other static memories. At the same time, the "/R cell type static memory is also required to have low power characteristics at rest. The current consumption in the E/R cell is
It is determined by the resistance value of polysilicon 12. Polysilicon that has not been doped with impurities has a layer resistance of about 100 GQ/hole. Further increasing this value is due to the resistance of polysilicon and heavy metals originally contained in 4e silicon. This is extremely difficult because it requires highly precise control of impurities, and it is thought that this pursuit has already reached its limit. It is obvious that as the degree of integration continues to increase, it will become difficult to maintain a sufficient resistance length within a cell in terms of area. That is, as the degree of integration continues to increase in the prior art, there is a problem in that the current consumption of the memory device increases as the degree of integration increases.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is aimed at increasing the effective resistance length of a high-resistance element. The present invention aims to provide a semiconductor device that can improve the above-mentioned conventional problems by eliminating the impurity diffusion region from the portion below the buried contact, which is one of the causes of shortening the semiconductor device.

[Summary of the invention]

As mentioned in the previous section, it has an effective high resistance length. If the length of impurity diffusion from both ends of the second polysilicon layer, .

In particular, since the first polysilicon layer contains sufficient impurities, the diffusion length of the impurities from the first polysilicon to the second polysilicon through the buried contact hole reaches several microns. In the present invention, a high melting point metal or its silicide, which acts as a barrier to diffusion phenomena for impurities, is buried in the buried contact, and the high melting point metal or its silicide is sandwiched between the low resistance first silicon layer or the low resistance single layer. By connecting the crystalline silicon layer and the high-resistance second polysilicon layer, diffusion of impurities into the second polysilicon layer is eliminated, thus reducing the effective high-resistance length L.
0 can be "L0+L,"K. High melting point metals such as tungsten and their silicides can make ohmic contact with silicon, polysilicon, and other metals.
Moreover, the diffusion rate of impurities into the high melting point metal is extremely low.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
Figures 1 and 2 are examples of the case where the present invention is applied to a high-resistance polysilicon load type static memory. FIG. 2 is a cross-sectional configuration diagram. Since these are examples corresponding to FIGS. 4 and 5, corresponding parts will be given the same reference numerals and explanations will be omitted, and only the characteristic parts will be explained. This embodiment is characterized by the second high resistance polysilicon 12 and the first low resistance polysilicon 12. High melting point gold m 31 such as tungsten is selectively buried in the buried contact hole with silicon 11 using a known method in which a high melting point metal is deposited only on the exposed portions of silicon. By making an ohmic connection between the first polysilicon and the second polysilicon by sandwiching the high melting point metal 3 in this way, the 1s9 IJ silicon 11
It is possible to eliminate the disadvantage that existed in the prior art that the effective high resistance length L0 of the second polysilicon 12 is reduced due to the high concentration impurities being diffused into the second polysilicon 12. As a method of depositing a high melting point metal only on the exposed portion of silicon, there is a method described in the literature rT, Mo
riya, S, Shima, Y, Ha
zuki, M.

Chiha, and M, Kashiwagi
, “A PLANARMETALLIZATIO
N PROCESS-ITS APPLICATION
NTo TRI-LEVEL ALUMINIJM
INTERCONNECTION”.

IEDM Dig, Tech, Papers
Dec, 1983. P.P.

550-553'', etc.

As is clear from comparing FIG. 2 and FIG. L0 is longer by L2 than the conventional example, so it is possible to form a higher resistance element in the same area.Also, high melting point metals such as tungsten can be used with silicon, polysilicon, and other metals. Omi with etc. □
'Knocking touch is possible.

Note that the present invention is not limited to the above embodiments, and can be applied in various ways. For example, in the embodiment, a high melting point metal is used as the barrier metal 31, but its silicide may also be used. Furthermore, although a case has been described in which low-resistance polysilicon 11 is used as the object to be contacted with doped silicon stubs, the present invention can also be applied to a case where low-resistance single-crystal silicon is used.

〔Effect of the invention〕

As explained above, according to the present invention, a high-melting point metal or its silicide is inserted into the buried 9 contact hole to prevent impurities from diffusing into the high-resistance polycontainer. A semiconductor device having advantages such as being able to prevent a decrease in resistance value can be provided.

[Brief explanation of the drawing]

Fig. 1 is a plan view of an isometric turn showing an embodiment of the present invention, Fig. 2 is a cross-sectional configuration diagram taken along the line ■-■ in Fig. 1, and Fig. 3 is a circuit of a high resistance load type static memory cell. 4 is a pattern plan view of the same cell, and FIG. 5 is a sectional view taken along the line V-V in FIG. 4. 11: Low resistance silicon layer, 12: High resistance silicon layer, 3: High melting point metal. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 4 Figure V

Claims (1)

[Claims] A refractory metal or its silicide is placed in a contact hole connecting the first polycrystalline silicon layer or low-resistance single-crystalline silicon layer containing impurities and the second polycrystalline silicon layer not containing impurities forming a high-resistance element. By sandwiching the high melting point metal or its silicide, the first
A semiconductor device characterized in that a polycrystalline silicon layer or a single crystalline silicon layer and a second polycrystalline silicon layer are connected.