JPS6151747U - - Google Patents

Info

Publication number
JPS6151747U
JPS6151747U JP1984135763U JP13576384U JPS6151747U JP S6151747 U JPS6151747 U JP S6151747U JP 1984135763 U JP1984135763 U JP 1984135763U JP 13576384 U JP13576384 U JP 13576384U JP S6151747 U JPS6151747 U JP S6151747U
Authority
JP
Japan
Prior art keywords
semiconductor chip
frame
main surface
thick film
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984135763U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984135763U priority Critical patent/JPS6151747U/ja
Publication of JPS6151747U publication Critical patent/JPS6151747U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Description

【図面の簡単な説明】
第1図は本考案の実施例の厚膜混成集積回路を
示す平面図、第2図は第1図の厚膜混成集積回路
を示す断面図、第3図は従来の厚膜混成集積回路
を示す断面図である。 尚図において、1……半導体チツプ、2……電
極引き出しリード、3……コーテイング剤、4…
…導体パターン、5……保護ガラス、6……基板
、7……エポキシ樹脂の帯状わく、8……保護ガ
ラスの帯状わく。

Claims (1)

    【実用新案登録請求の範囲】
  1. 厚膜基板の主面上に半導体チツプが設けられ、
    前記半導体チツプを覆うコーテイング剤の流出を
    防止するように前記半導体チツプの周囲の前記主
    面にわくが設けられ、前記わく外の前記主面に絶
    縁性の保護膜が設けられた厚膜混成集積回路にお
    いて、前記わくが前記保護膜と同様な材料からな
    ることを特徴とする厚膜混成集積回路。
JP1984135763U 1984-09-07 1984-09-07 Pending JPS6151747U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984135763U JPS6151747U (ja) 1984-09-07 1984-09-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984135763U JPS6151747U (ja) 1984-09-07 1984-09-07

Publications (1)

Publication Number Publication Date
JPS6151747U true JPS6151747U (ja) 1986-04-07

Family

ID=30694246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984135763U Pending JPS6151747U (ja) 1984-09-07 1984-09-07

Country Status (1)

Country Link
JP (1) JPS6151747U (ja)

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