JPS6150423A - Digital-analog converter - Google Patents

Digital-analog converter

Info

Publication number
JPS6150423A
JPS6150423A JP17279284A JP17279284A JPS6150423A JP S6150423 A JPS6150423 A JP S6150423A JP 17279284 A JP17279284 A JP 17279284A JP 17279284 A JP17279284 A JP 17279284A JP S6150423 A JPS6150423 A JP S6150423A
Authority
JP
Japan
Prior art keywords
frequency
signal
dither
digital
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17279284A
Other languages
Japanese (ja)
Inventor
Tetsuaki Araki
徹朗 荒木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teac Corp
Original Assignee
Teac Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teac Corp filed Critical Teac Corp
Priority to JP17279284A priority Critical patent/JPS6150423A/en
Publication of JPS6150423A publication Critical patent/JPS6150423A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To improve the accuracy of D/A conversion by applying over-sampling to a digital signal to be subject to D/A conversion at a frequency nf so as to improve the frequency-phase characteritic at a signal having high frequency and subtract sufficiently dither up to a high frequency. CONSTITUTION:A digital signal of sampling frequency (f) and bit number N is inputted from a terminal 1 and a sampling pulse in a frequency nf being n-time of the frequency (f) is inputted from a terminal 4. An over-sampling circuit 2 applies over-sampling in frequency nf to the input signal. A dither from a dither generator 5 is sampled in the frequency nf similarly by an A/D converting circuit 6 to form a digital signal and the both are superimposed by an adder 3. An output signal of the adder 3 is converted into an analog signal by the 1st D/A conversion circuit 7 having (N+K)-bit more than the N-bit in bit number. A signal obtained by converting into an analog signal at the 2nd D/A converter circuit 8 from the digitize dither is subtracted from the signal converted into the analog signal by a subtractor 9 and the analog signal subtracted with the dither is obtained at a terminal 10.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はディジタル信号の処理方法に間するもので、デ
ィジタル信号をアナログ信号に変換するディジタル−ア
ナログ変換(D/A変換)装置の精度を向上させる方法
として知られているディザと呼ばれる白色性雑音をディ
ジタル信号に重畳しD/A変換変換算減算方法の改良に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for processing digital signals, and improves the accuracy of a digital-to-analog conversion (D/A conversion) device that converts a digital signal into an analog signal. The present invention relates to an improvement of a D/A conversion, calculation, and subtraction method in which white noise called dither is superimposed on a digital signal.

従来の技術 ディジタル信号の処理におけるD/A変換の精度を向上
させる技術は従来より大きな課題になっており、回路的
に種々の改良が試みられてきたが十分に精度を向上させ
たものが得られなかった。
Conventional technology The technology to improve the accuracy of D/A conversion in digital signal processing has been a major issue than before, and various circuit improvements have been attempted, but none have achieved sufficient accuracy. I couldn't.

例えばディジタル信号処理におけるいわゆる量子化雑音
を白色性雑音とするために、ディジタル信号にディザと
呼ばれる白色性雑音を重畳させてD/A変換後ディザを
減算する処理方法が知られているが、この方法はサンプ
リング周波数が十分高くないと高い周波数における位相
特性が悪化するためディザの減算時に高い周波数におい
て完全な減算をすることが不可能となり高精度なり/A
変換が出来ないという大きな欠点を有している。
For example, in order to convert so-called quantization noise in digital signal processing into white noise, a processing method is known in which white noise called dither is superimposed on the digital signal and the dither is subtracted after D/A conversion. The method is that if the sampling frequency is not high enough, the phase characteristics at high frequencies will deteriorate, making it impossible to perform complete subtraction at high frequencies during dither subtraction, resulting in high precision./A
The major drawback is that it cannot be converted.

実施例 本発明はD/A変換における前記欠点をなくしたもので
、以下量→図を参照して本発明の実施例に係わるD’/
A変換v2@について述べる。年4図において(1)か
らサンプリング周波数f、ビット数Nのディジタル信号
が入力する。(4)からは周波数fのn倍の周波数nf
のサンプリングパルスが人力する。オーバーサンプリン
グ回路(2)で前記ディジタル信号を周波数nfでオー
バーサンプリングする。ディザ発生器(5)からのディ
ザをD/A変換回路(6)で同じく周波数nfでサンプ
リングしてディジタル信号とし、このディジタル化した
ディザと前記オーバーサンプリングした信号とを加算器
(3)で重畳させる。加算器(3)の出力信号をNビッ
トよりビット数の多いN+Kビットの第1のD/A変換
回路(7)でアナログ信号に変換する。ここでNビット
よりビット数の多いD/A変換回路でアナログ信号に変
換するのは、加算器(3)でオーバーサンプリングした
信号とディジタル化したディザを重畳させたためである
が、通常Nビットより1ビット多いN+1ビツトのD/
A変換回路で十分である。前記第1のD/A変換回路(
7)でアナログ信号に変換した信号から、ディジタル化
したディザな第2のD/A変換回路(8)でアナログに
変換した信号を減算器(9)で減算させると、(lO)
にディザが減算されたアナログ信号が得られる。
Embodiment The present invention eliminates the above-mentioned drawbacks in D/A conversion.
A conversion v2@ will be described. In Figure 4, a digital signal with sampling frequency f and number of bits N is input from (1). From (4), the frequency nf is n times the frequency f.
The sampling pulse is manually generated. An oversampling circuit (2) oversamples the digital signal at a frequency nf. The dither from the dither generator (5) is sampled at the same frequency nf by the D/A conversion circuit (6) to form a digital signal, and this digitized dither and the oversampled signal are superimposed by the adder (3). let The output signal of the adder (3) is converted into an analog signal by a first D/A conversion circuit (7) of N+K bits, which has more bits than N bits. Here, the reason why the D/A conversion circuit with more bits than N bits converts it into an analog signal is because the oversampled signal and the digitized dither are superimposed in the adder (3), but normally the number of bits is more than N bits. 1 bit more N+1 bit D/
An A conversion circuit is sufficient. The first D/A conversion circuit (
When the subtracter (9) subtracts the signal converted to analog by the digitized dithered second D/A conversion circuit (8) from the signal converted to analog signal in step 7), (lO) is obtained.
An analog signal with dither subtracted is obtained.

発明の効果 上述から明らかな如く、D/A変換するディジタル信号
を周波数nfでオーバーサンプリングしであるため、信
号の高い周波数における周波数位相特性が良好となリデ
ィザの減算が高い周波数まで十分に行われる。このため
D/A変換の精度をいちじるしく向上させることが可能
となり、高性能なり/A変換1置を提供することが出来
る。
Effects of the Invention As is clear from the above, since the digital signal to be D/A converted is oversampled at the frequency nf, the frequency phase characteristics at high frequencies of the signal are good, and redither subtraction is sufficiently performed up to high frequencies. . Therefore, it is possible to significantly improve the accuracy of D/A conversion, and it is possible to provide a high-performance/A/A conversion system.

【図面の簡単な説明】[Brief explanation of drawings]

1図は本発明に係るディジタル−アナログ変換装置のブ
ロック図を示す。 2・・・・・オーバーサンプリング回路、3・・・・・
加算器、 5・・・−・ディザ発生器、6・・・・・ア
ナログ−ディジタル変換回路、7・・・・・第1のディ
ジタル−アナログ変換回路、8・・・・・第2のディジ
タル−アナログ変換回路、9・・・・・減算器。 手続補正書(自船 昭和(資)年3月14日
FIG. 1 shows a block diagram of a digital-to-analog converter according to the present invention. 2... Oversampling circuit, 3...
Adder, 5... Dither generator, 6... Analog-digital conversion circuit, 7... First digital-analog conversion circuit, 8... Second digital -Analog conversion circuit, 9...subtractor. Procedural amendment (March 14, 1920)

Claims (1)

【特許請求の範囲】 サンプリング周波数f、ビット数Nのディジタル信号を
n倍の周波数nfでオーバーサンプリングするオーバー
サンプリング回路と、 ディザ発生器と、 前記ディザ発生器からの出力ディザを周波数nfでサン
プリングするアナログ−ディジタル変換回路と、 オーバーサンプリングされた前記ディジタル信号と周波
数nfでサンプリングされた前記ディザとを加算する加
算器と、 前記加算器の出力信号をアナログ信号に変換する少なく
ともビット数がNビットより1ビット多いN+Kビット
の第1のディジタル−アナログ変換回路と、 周波数nfでサンプリングされた前記ディザをアナログ
信号に変換する第2のディジタル−アナログ変換回路と
、 前記第1のディジタル−アナログ変換回路の出力信号か
ら前記第2のディジタル−アナログ変換回路の出力信号
を減算する減算器と、 を備えていることを特徴とするディジタル−アナログ変
換装置。
[Claims] An oversampling circuit that oversamples a digital signal with a sampling frequency f and a number of bits N at a frequency nf that is n times higher; a dither generator; and a dither generator that samples output dither from the dither generator at a frequency nf. an analog-to-digital conversion circuit; an adder for adding the oversampled digital signal and the dither sampled at a frequency nf; a first digital-to-analog conversion circuit with N+K bits, which is one bit more; a second digital-to-analog conversion circuit for converting the dither sampled at a frequency nf into an analog signal; and a first digital-to-analog conversion circuit. A digital-to-analog conversion device comprising: a subtracter that subtracts the output signal of the second digital-to-analog conversion circuit from the output signal.
JP17279284A 1984-08-20 1984-08-20 Digital-analog converter Pending JPS6150423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17279284A JPS6150423A (en) 1984-08-20 1984-08-20 Digital-analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17279284A JPS6150423A (en) 1984-08-20 1984-08-20 Digital-analog converter

Publications (1)

Publication Number Publication Date
JPS6150423A true JPS6150423A (en) 1986-03-12

Family

ID=15948440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17279284A Pending JPS6150423A (en) 1984-08-20 1984-08-20 Digital-analog converter

Country Status (1)

Country Link
JP (1) JPS6150423A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612144A (en) * 1979-07-11 1981-02-06 Mitsubishi Electric Corp Dither
JPS58168323A (en) * 1982-03-29 1983-10-04 Yoshio Yamazaki Signal quantizing device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612144A (en) * 1979-07-11 1981-02-06 Mitsubishi Electric Corp Dither
JPS58168323A (en) * 1982-03-29 1983-10-04 Yoshio Yamazaki Signal quantizing device

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