JPS61501295A - ウェハスケールパッケージシステム - Google Patents

ウェハスケールパッケージシステム

Info

Publication number
JPS61501295A
JPS61501295A JP60500990A JP50099085A JPS61501295A JP S61501295 A JPS61501295 A JP S61501295A JP 60500990 A JP60500990 A JP 60500990A JP 50099085 A JP50099085 A JP 50099085A JP S61501295 A JPS61501295 A JP S61501295A
Authority
JP
Japan
Prior art keywords
wafer
header
ground
circuit
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60500990A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0584668B2 (https=
Inventor
ストツパー・ハーバート
パーキンス，コーネリアス・チヤーチル
Original Assignee
エンバィアロンメンタル・リサーチ・インスティテュート・オブ・ミシガン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エンバィアロンメンタル・リサーチ・インスティテュート・オブ・ミシガン filed Critical エンバィアロンメンタル・リサーチ・インスティテュート・オブ・ミシガン
Publication of JPS61501295A publication Critical patent/JPS61501295A/ja
Publication of JPH0584668B2 publication Critical patent/JPH0584668B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
JP60500990A 1984-02-21 1985-02-21 ウェハスケールパッケージシステム Granted JPS61501295A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58197584A 1984-02-21 1984-02-21
US581975 1984-02-21

Publications (2)

Publication Number Publication Date
JPS61501295A true JPS61501295A (ja) 1986-06-26
JPH0584668B2 JPH0584668B2 (https=) 1993-12-02

Family

ID=24327329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60500990A Granted JPS61501295A (ja) 1984-02-21 1985-02-21 ウェハスケールパッケージシステム

Country Status (3)

Country Link
EP (1) EP0174950A4 (https=)
JP (1) JPS61501295A (https=)
WO (1) WO1985003804A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400262A (en) * 1989-09-20 1995-03-21 Aptix Corporation Universal interconnect matrix array
US5377124A (en) * 1989-09-20 1994-12-27 Aptix Corporation Field programmable printed circuit board
EP0481703B1 (en) * 1990-10-15 2003-09-17 Aptix Corporation Interconnect substrate having integrated circuit for programmable interconnection and sample testing

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3657805A (en) * 1970-01-02 1972-04-25 Texas Instruments Inc Method of housing semiconductors
US3781683A (en) * 1971-03-30 1973-12-25 Ibm Test circuit configuration for integrated semiconductor circuits and a test system containing said configuration
GB1487945A (en) * 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
US3983479A (en) * 1975-07-23 1976-09-28 International Business Machines Corporation Electrical defect monitor structure
US4246595A (en) * 1977-03-08 1981-01-20 Matsushita Electric Industrial Co., Ltd. Electronics circuit device and method of making the same
US4257061A (en) * 1977-10-17 1981-03-17 John Fluke Mfg. Co., Inc. Thermally isolated monolithic semiconductor die
US4220917A (en) * 1978-07-31 1980-09-02 International Business Machines Corporation Test circuitry for module interconnection network
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
EP0069762B1 (en) * 1981-01-16 1989-02-08 JOHNSON, Robert Royce Universal interconnection substrate
US4484215A (en) * 1981-05-18 1984-11-20 Burroughs Corporation Flexible mounting support for wafer scale integrated circuits

Also Published As

Publication number Publication date
WO1985003804A1 (en) 1985-08-29
EP0174950A1 (en) 1986-03-26
JPH0584668B2 (https=) 1993-12-02
EP0174950A4 (en) 1988-02-05

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