JPS6148716A - Encoder - Google Patents

Abstract

PURPOSE:To detect a position in case of abrupt variation accurately by applying neither of a forward and a backward turn signal when both signals are outputted at the same time, and adding and outputting a plus or minus signal according to a forward or backward turn signal generated at next timing. CONSTITUTION:When an A-phase signal SA1 precedes a B-phase signal SB1 in phase by 90 deg., rotation stops or slows down greatly, and if the signal SA1 and SB1 vary between clock pulses (a) and (b) when sudden rotation is caused by an impact, etc., at a low oscillation frequency of clock pulses CLK0, there is no clock pulse and forward rotation is not be detected, so that neither SU nor SD is outputted. The AND gate of a circuit 14 outputs a signal showing double pulse generation to a calculating circuit 108. Consequently, the circuit 108 sends a signal to an oscillator 100 so as to increase the oscillation frequency of clock pulses, and then the frequency of CLK0 increases and forward rotation is detected correctly, so that stored contents are added as a forward rotation signal and outputted.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a rotary engine.

[Conventional technology]

Rotary encoders that reduce the power consumption in the electric circuit of optical or magnetic date-tally encoders have already been proposed (for example, Japanese Patent Application Nos. 59-73868 and 59-73871, which were proposed in conjunction with the present application).
No. 59-73872). FIG. 2 shows a circuit diagram of these encoders. The electric circuit 10 of the encoder includes an oscillation circuit 100 that generates a clock pulse CLKO, and a circuit driving clock pulse CLKi generated in response to the falling edge of the clock pulse CLKO. a monostable multivibrator 101 that makes the signal tm of the photodiodes 4 and 5
103, A phase signal SA and B phase signal S from the amplifier circuit
A rising/falling detection circuit consisting of D-type slip-flops FFI to FF4 and a decoder DECDR connected as shown in the figure for detecting the rising or falling vyx of B 4. Increased signal S from the detection circuit; , or an or game for guiding the decrease signal SD to the up/down counter 107) 105
．． 106 are connected as shown. The power source of the light emitting diode 9 as the light source of the encoder is the clock pulse C.
It is engineered into LK0. Therefore, the light emitting diode 9 is not always turned on as before, but by the clock pulse CLK.

Lights up only when is at a high level, and the human face transmitted through the rotating slit plate and detected by photodiode 4.5, B
The phase signal also corresponds to the clock pulse CLK0, and the battery 11 is connected as a power source to these circuits.
The power consumption is very small.

The operation of the above circuit will be described below.

The exemplary circuit of the rising/falling detection circuit 104 of FIG.
Illustrated in the figure. That is, D type flip 70 tube FFI~
FF4 and a NAND gate Gl that receives these outputs,
G7, G8, G14 and G2°G4. G11. G1
3 are connected as shown in the figure. The FFI is connected to the A-phase signal Sλ, and the FF3 is connected to the B-phase signal SB, and the signals of these flip-flops 5Ai=2''1sA1=2'l
5B1=2" l5B2=23. Then,
As shown in Fig. 4, the shaft rotates forward and SA becomes SB work υ9.
If the 0° phase is leading (Fig. 4 ID), El
), gate Gl, G7. G8. An increase signal Su is output via G14i. On the other hand, when the shaft is reversed, gate G2. G4. G11. A decrease signal So is output via G13.

Furthermore, in the above-mentioned encoder, in order to further reduce power consumption, the above-mentioned S, J, SD
signal? Calculate the timing at which these signals occur by inputting them, and if the generation cycle of these signals is low, use the clock pulse C.
Circuit 1081F that lowers the oscillation frequency of LK0! : Provided. In other words, if the rotation of the encoder shaft decreases and the position of the shaft can be detected even with a low-frequency clock pulse, using a low frequency means that the lighting time of the light-emitting diode 9 per fixed time will be shortened or shortened. Power consumption is reduced.

[Problem that the invention seeks to solve]

Generally, the rotation of the shaft changes continuously when it increases or decreases, so even if the frequency of the clock pulse is changed according to the rotation of the shaft as described above, the position can usually be detected without any problem, and the power consumption will be further reduced. can be reduced. Even when changing the secondary station wave number, a considerable margin is provided, and there is no problem even if the rotational speed changes from a decreasing state to an increasing state. However, when a sudden change occurs that exceeds what is normally expected, for example, a shaft that is rotating at a low speed or is stopped suddenly rotates instantaneously due to an impact, and in response to that rotation, the shaft rotates forward (increases). ) When the clock pulse CLK does not exist between the timings of detecting the signal SU or the reversal (decrease) signal SD, the rising/falling detection circuit 104 shown in FIG.
As shown in (k), each game) G7. Output SU and SD from G4 at the same time.

Therefore, a problem arises in that it is treated as if it did not rotate at this moment. The above error is considered unacceptable due to the positioning accuracy required of the encoder.

[Tth means to solve the invention]

The present invention includes a transmitting element that responds to clock pulses, a first and a second transmitting element that are provided opposite to the transmitting element, and that are provided to output a predetermined angular difference signal in response to rotation of the rotary plate. a receiving element, a rising/falling detection circuit that detects the rising or falling of the output signals of the first and second receiving elements and outputs a normal rotation or reverse rotation signal in response to the rotation of the rotary plate; and the normal rotation. Alternatively, an encoder is provided with a counter for counting the reverse rotation signal and is configured to change the oscillation frequency of the clock pulse in response to the generation cycle of the forward rotation or reverse rotation signal, wherein the forward rotation and reverse rotation signals are output simultaneously. In this case, neither signal is applied to the counter, and one of the above signals is added and output according to the forward rotation or reverse rotation signal generated at the next timing, and a pulse correction circuit is provided. ? An encoder is provided having the following characteristics.

[For production]

That is, in the present invention, when forward rotation and reverse rotation signals are output at the same time, neither signal is applied to the counter at that time, and at the same time, the existence of the forward rotation and reverse rotation signals is memorized.

In such a case, the oscillation frequency of the clock pulse is increased, and forward or reverse rotation can be accurately detected in the next cycle. If the next cycle is detected as normal rotation due to the continuity of rotation, the stored t contents are added as a normal rotation signal and output.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 illustrates an electric circuit section of an optical rotary encoder as an embodiment of the present invention. As is clear from the figure, in the electric circuit of the present invention, a pulse correction circuit 110 is provided between the or game) 1t) 5.106 and the up/down counter 107, and the forward rotation signal Su or the reverse rotation signal S
0, which outputs the corrected signal C8, J or C8D', is the same as in FIG. 2.

[Pulse Correction Circuit] An embodiment of the IO is illustrated in FIG. A pulse correction circuit 110 shown in FIG. 8g6, AND gates 10 and 11, OR gates 12 and 13, a missed pulse detection circuit 14, a timing detection circuit 15, a direction detection circuit 16, and a correction circuit 17 are connected as shown.

FIG. 8 shows a circuit example in which the circuit shown in FIG. 7 is more specifically realized.

The AND gates 10 and 11 and the OR gates 12 and 13 are the same as those shown in FIG. 7. As the miss pulse detection circuit 14, an AND gate 141 and an inverter 142 are connected as shown. timing detection circuit 15, correction circuit 17,
The direction detection circuit 16 includes OR gates 151% JK flip frogs 171 to 173 and AND gates 174 and 175.
゜177, 178, 179, inverter 176, and J
K-clip 70 tab 161 is connected as shown.

The seventh factor and the entire operation of the pulse correction circuit 110 shown in FIG. 8 will be explained.

First, a normal case will be described. In this case, since only one of the S, J, and SD signals exists, the output 1rOJ of the AND gate 141 becomes 1, and the output 514 of the next miss pulse detection circuit 14 becomes 1 via the inverter 142. Therefore, if there is a Su signal, C8o in the same state as eight is outputted via the AND gate 10 and the OR gate 12. That is, in the normal case, the forward rotation or reverse rotation signal is output as is without being corrected as before.

Next, a case where pulse correction is required will be described with reference to FIG.

Figure 9 is a timing diagram when the human phase signal SAI (Figure 9 (ml) is the B phase signal 5BI (Figure 9 (b)) and the phase is ahead. By the way, if the oscillation frequency of the clock pulse CLKo is low due to the decrease in the oscillation frequency yt'', if the rotation starts suddenly due to an impact etc.
A1. When there is a change in SB1, normal rotation could be detected if clock pulse a' was present, but normal rotation could not be detected and SD was output along with So at clock pulse b. Since the output 514 of the detection circuit 14 becomes 0, neither C3tI nor C8D is output.

The AND gate 141 outputs a signal 314a indicating that there is an overlapping pulse to the oscillation frequency calculation circuit 108. In response to this, the processing circuit 108 issues two signals to the oscillator 100 that increases the oscillation frequency of the clock pulse, and the frequency of the clock pulse CLK0 increases (clock pulse CLK
o C → d).

Normal rotation is correctly detected at C of the next clock pulse CL Ko . In this case, 5U=1.5o=0, so C
Only 8U is output. Also, the existence of duplicate pulses is set in the JK flip-flop 171, and the output F3'=
rlJ (Fig. 9(f)).

Furthermore, at d of the next clock pulse CLKo, since all inputs of the ant game 1740 are "L", the JK flip 70 knob 172 is set, and the output F4 becomes 1 (
Figure 9(g)).

At e of clock pulse CL, 0, SU is "
1'', and C3tI is output as is.

In this case, the output of the NOR gate 176 = r [) J, so the output of the AND gate 177 is rOJ, so JK
Flip-flop 173 remains unset.

At f of the clock pulse CLKQ, when Su:ro'', Re=o, 5D=o, and the output of the OR) 151 becomes ``0'', the output of the NOR gate 176 becomes ``1'',
The output of AND gate 177 becomes "1", and the input of AND gates 178 and 179 becomes "1". On the other hand, JK7
Since the lip flop 161 previously had 5LI=1, 5D=0, the Q output=1, and only from the AND gate 178
1" is output to the OR gate 12, and C8U is shown in Figure 9)
The output is continued in the L direction shown by the intersection lines. That is, the inverter 176 is used to detect idle time, and during this idle time, the contents stored in the flip-flop are output in accordance with the direction specified by the JK flip-flop 161. Output = “1”
Accordingly, the JK flip-flop 173 is set, the output of the AND gate 175 becomes "1", and the JK flip 70 knobs 171 and 172 are reset to 0. After that, the counting is performed normally as in the conventional case.

Although the above embodiments have been described for optical rotary encoders, they are for magnetic rotary encoders.
The same is true.

〔Effect of the invention〕

As described above, according to the present invention, in order to further reduce the power consumption of the electric circuit of the encoder, the frequency of the ring pulse can be made variable, and when LF>rapid rotation axis This makes it possible to accurately detect the positional quality f at the time of the change even if the change in f is a bit different. Although there will be some time delay in detecting a positional change when there is a sudden change, this does not pose a problem in use.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram of an encoder as an embodiment of the present invention, FIG. 2 is an electric circuit diagram of a conventional encoder, FIG. 3 is a rise/fall detection circuit diagram of the circuit in FIG. Figure and 5th
The figure is an operation timing diagram of the circuit in Figure 3, Figure 6 is a timing diagram showing the generation of erroneous pulses in the circuit in Figure 3, Figure 7 is a block diagram of the pulse correction circuit of the circuit in Figure 1, and Figure 8 is a diagram of the pulse correction circuit in the circuit in Figure 1. FIG. 9 is a detailed circuit diagram of the circuit shown in FIG. 9, and a diagram showing the operation timing of the circuits of FIGS. 1, 7, and 8. (Explanation of symbols) 100: Oscillation circuit, 101: Monostable multivibrator, 102.103: Old amplifier circuit, 104: Rising/falling detection circuit, 11)5
, 11J6... Or Gate, 107...
・Up/down counter, 108...Oscillation frequency calculation circuit, 11()・Old...Pulse correction circuit, 10
, 11...and gate, 12.13...
... OR gate, 14 ... Miss pulse detection circuit, 15 ... Timing detection circuit, 16 ... Direction detection circuit, 17 ... Correction circuit. Figure 4(b) to CL. 1 analffi north (c) CL, `` soil ■ old Yu (e) SS - '' north m (f) SAI '' -- hee'' (g) SA2 -1111 (h) Sa] -1 ``- 1 Sea (n') 582 - "-1110I G7 G8 G14 Fig. 5 (b) CLKo-Concave ■" North concave - (c) CLK + W Sat ■7'' (e) SB North U stop --Kita (f) 5A1-"-Itto (9) SA2--"--]- (h) 581"-Ichiri m- (Le) SB2-"-111102 04
G11 G13 Fig. 6 (Q) f-1to''-- (b) CL to 〇 -几-U-Masu (c) CL to l-1-''-1[-Sat (d) SA
-■------■ (e) SB -11 Rouu (f) SAT -11-Cho 111 (g) 5A2
L (h)SB+ -1111--- (i) 582 L (k)So---1-''-1 Fig. 7

Claims (1)

[Claims] 1. A transmitting element responsive to a clock pulse; first and second receiving elements disposed opposite the transmitting element and outputting a predetermined angular difference signal in response to the rotation of the rotating plate; a rising/falling detection circuit that detects the rising or falling of the output signals of the first and second receiving elements and outputs a forward or reverse rotation signal in response to the rotation of the rotary plate; the forward or reverse rotation signal; The encoder is equipped with a counter that counts the clock pulses, and is configured to change the oscillation frequency of the clock pulse in response to the generation cycle of the forward rotation or reverse rotation signal, and when the forward rotation and reverse rotation signals are output simultaneously, the encoder It is characterized by being provided with a pulse correction circuit that does not apply any signal to the counter, but adds and outputs one of the above signals according to the forward rotation or reverse rotation signal generated at the next timing. , encoder.