JPS6148668B2 - - Google Patents
Info
- Publication number
- JPS6148668B2 JPS6148668B2 JP5242279A JP5242279A JPS6148668B2 JP S6148668 B2 JPS6148668 B2 JP S6148668B2 JP 5242279 A JP5242279 A JP 5242279A JP 5242279 A JP5242279 A JP 5242279A JP S6148668 B2 JPS6148668 B2 JP S6148668B2
- Authority
- JP
- Japan
- Prior art keywords
- potential
- electrometer
- grid
- electrode
- zero
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 8
- 230000001360 synchronised effect Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Control Or Security For Electrophotography (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
【発明の詳細な説明】
本発明は例えば電子複写機の感光ドラム表面の
潜像電位を検知するための改良された表面電位計
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved surface electrometer for detecting latent image potential on the surface of a photosensitive drum of, for example, an electronic copying machine.
従来の電位計の特性を第1図に示す。従来の表
面電位計では実際の表面電位と電位計の検知出力
との関係が第4図の如く0電位付近の原点を通ら
ず、そのためこのオフセツト現象をキヤンセルす
べく、電位計の測定回路を工夫していた。しかし
回路構成が複雑であつたり、較正を要したりする
欠点があつた。 Figure 1 shows the characteristics of a conventional electrometer. In conventional surface electrometers, the relationship between the actual surface potential and the detection output of the electrometer does not pass through the origin near zero potential as shown in Figure 4. Therefore, in order to cancel this offset phenomenon, the measurement circuit of the electrometer was devised. Was. However, there were drawbacks such as a complicated circuit configuration and the need for calibration.
本発明はこのような欠点を除去し、電位計の取
扱いを容易にするもので、電位プローブの検知窓
にグリツドを設けたこと及びそのグリツドにバイ
アス印加して、実際の表面電位と検出出力との関
係が原点を通るようにしたことを特徴とする。 The present invention eliminates these drawbacks and facilitates the handling of the electrometer by providing a grid in the detection window of the potential probe and applying a bias to the grid, thereby making it possible to compare the actual surface potential with the detection output. It is characterized in that the relationship passes through the origin.
第1−1図は表面電位計の窓部部分平面図、第
1−2図はその部分の断面図である。図中1は表
面電位計の金属ケース、2は電位検知のための開
口窓、3はガラスエポキシ樹脂でできた、ケース
に設けたグリツド支持用の窓わく、4はタングス
テンを金メツキした金属細線から成るグリツド、
5は開口窓2を開閉するための一定速度で回転す
る金属羽根、6は電位検知用の固定電極である。
本体1及び回転羽根5は電気的に接地されてい
る。 FIG. 1-1 is a plan view of a window portion of the surface electrometer, and FIG. 1-2 is a sectional view of that portion. In the figure, 1 is a metal case of the surface electrometer, 2 is an opening window for potential detection, 3 is a window frame made of glass epoxy resin for supporting the grid, and 4 is a thin metal wire made of gold-plated tungsten. A grid consisting of
5 is a metal blade that rotates at a constant speed for opening and closing the opening window 2, and 6 is a fixed electrode for potential detection.
The main body 1 and the rotating blade 5 are electrically grounded.
第2図は電位測定回路例で、第1図と同一の構
成部分を同一の番号で示す。他に7は回転羽根5
を回転させるためのモータ、8,9,10は電極
6に対する入力インピーダンスを高めるための
FETによるバツフアで9は抵抗値100MΩの抵抗
器、8はFET、10はソース抵抗である。11
はFET8のソース出力を必要な大きさに増幅す
るための交流増幅器、16は同期クランプ回路で
同期信号増幅器15の出力によつて同期クランプ
する。尚、同期信号は発光素子12と対向して設
けた受光素子13と回転羽根5に設けた光路14
とで得ている。つまり光路14は回転羽根5が開
口窓2を閉じた時に開く様になつており、12か
らの光が13で受光されタイミング信号が出力さ
れる。17はクランプ出力を積分する回路、18
は出力端子である。 FIG. 2 shows an example of a potential measuring circuit, in which the same components as in FIG. 1 are designated by the same numbers. The other 7 is the rotating blade 5
motors 8, 9, and 10 for increasing the input impedance to the electrode 6;
In the buffer by FET, 9 is a resistor with a resistance value of 100MΩ, 8 is a FET, and 10 is a source resistance. 11
16 is an AC amplifier for amplifying the source output of FET 8 to a required magnitude; 16 is a synchronous clamp circuit that performs synchronous clamping using the output of the synchronous signal amplifier 15; Note that the synchronization signal is transmitted through the light receiving element 13 provided opposite the light emitting element 12 and the optical path 14 provided in the rotary blade 5.
I am getting it. That is, the optical path 14 is opened when the rotary blade 5 closes the aperture window 2, and the light from 12 is received by 13 and a timing signal is output. 17 is a circuit that integrates the clamp output; 18
is the output terminal.
いま、表面電位計のケース1の開口部2を被測
定対称物表面に接近させると、電極6と被測定対
称物との間に電界が誘起する。その電界を回転羽
根5で断続すると、電極6に電界の強さにその振
幅が比例した微弱な交流信号が誘起する。電界の
正、負を判別するために回転羽根5が開口窓2を
閉じた瞬間を電位が零であると定義する。そのた
めに回転羽根5が開口窓2を閉じた瞬間に開く光
路14によつて同期信号が作られ、同期クランプ
回路16によつて増幅器11からの交流信号を一
瞬零にクランプする。その零を基準に波形を積分
器17で積分すれば、出力端子18に被測定対称
物の表面電位に比例した直流出力が得られる。 Now, when the opening 2 of the case 1 of the surface electrometer is brought close to the surface of the object to be measured, an electric field is induced between the electrode 6 and the object to be measured. When the electric field is interrupted by the rotating blade 5, a weak alternating current signal whose amplitude is proportional to the strength of the electric field is induced in the electrode 6. In order to determine whether the electric field is positive or negative, the moment when the rotary blade 5 closes the aperture window 2 is defined as zero potential. For this purpose, a synchronous signal is generated by the optical path 14 which opens at the moment when the rotary blade 5 closes the aperture window 2, and the synchronous clamp circuit 16 momentarily clamps the alternating current signal from the amplifier 11 to zero. If the waveform is integrated by the integrator 17 using the zero as a reference, a DC output proportional to the surface potential of the object to be measured is obtained at the output terminal 18.
ところが第2図において、被測定対称物の表面
電位が零の場合でも波形が無くなることはなく電
極6にはわずかな残留波形が残り、従つて出力1
8は零にはならない。この原因としてFET8の
ゲート漏れ電流が考えられる。 However, in FIG. 2, even when the surface potential of the object to be measured is zero, the waveform does not disappear and a slight residual waveform remains on the electrode 6, so that the output 1
8 cannot be zero. The cause of this is thought to be the gate leakage current of FET8.
今電極6とケース1との静電容量の最大値をC
MAX、最小値をCMIXとし、抵抗9の抵抗値をR9
とし、FET8のゲート漏れ電流をIGとすれば電
極6のオフセツト電位E0は
E0=IG・R9 (1)
電極6にあらわれる残留電位のピーク振幅値△
Eは
△E=CMAX−CMIN/(CMAX+CMIN)/
2・E0(2)
=CMAX−CMIN/(CMAX+CMIN)/2
・IG・R9(3)
となる。 Now, the maximum value of capacitance between electrode 6 and case 1 is C
MAX , the minimum value is C MIX , and the resistance value of resistor 9 is R 9
If the gate leakage current of FET 8 is I G , then the offset potential E 0 of the electrode 6 is E 0 = I G・R 9 (1) The peak amplitude value of the residual potential appearing at the electrode 6 △
E is △E=C MAX - C MIN / (C MAX + C MIN )/
2・E 0 (2) = C MAX − C MIN / (C MAX + C MIN )/2
・I G・R 9 (3).
具体的数値として、CMIN=1.793PF,CMAX=
1.896PF,IG=1nA,R9=100MΩとすると、
△E=1.896−1.793/(1.896+1.
793)/2
×1×10-9×100×10-6
=5.6mVp-p (4)
となり、約5.6mVp-pの残留電圧が電極6に乗る
ことになる。 As concrete numbers, C MIN = 1.793PF, C MAX =
1.896PF, I G = 1nA, R 9 = 100MΩ, △E = 1.896-1.793/(1.896+1.
793)/2 × 1 × 10 -9 × 100 × 10 -6 = 5.6 mV pp (4), and a residual voltage of about 5.6 mV pp will be applied to the electrode 6.
従つて、第2図の回路において、FET8のゲ
ート漏れ電流による電極6の電位オフセツトは正
である。本例ではグリツト4に負電位を加えるこ
とによつて残留電圧を打消すことができた。その
大きさは外ケース1の開口窓2の部分において、
電極6から外ケース1の内面に相当する面の空間
電位が零になる様な値を印加すれば良い。以上の
例においてはグリツド4に印加する電圧が−
2.2Vのとき、表面電位と出力電圧との関係が第
4図から第3図の如き好結果となり、残留電圧は
約4分の1に減小した。 Therefore, in the circuit of FIG. 2, the potential offset of the electrode 6 due to the gate leakage current of the FET 8 is positive. In this example, the residual voltage could be canceled by applying a negative potential to the grit 4. The size of the opening window 2 of the outer case 1 is as follows:
A value may be applied from the electrode 6 such that the space potential of the surface corresponding to the inner surface of the outer case 1 becomes zero. In the above example, the voltage applied to grid 4 is -
At 2.2V, the relationship between the surface potential and the output voltage showed good results as shown in FIGS. 4 to 3, and the residual voltage was reduced to about one-fourth.
本例にてグリツド細線4の直径は60ミクロン、
線間ピツチは1mmにおいて好結果が得られたが、
必ずしも線間ピツチは1mmである必要はなく、ま
た、平行細線でなく網目状の導体を用いても同様
の効果が得られる。 In this example, the diameter of the grid wire 4 is 60 microns.
Good results were obtained with a line pitch of 1 mm, but
The line pitch does not necessarily need to be 1 mm, and the same effect can be obtained even if a mesh conductor is used instead of parallel thin lines.
第5図はグリツドとケース1との間隔と零補正
の為の最適グリツドバイアス電圧との関係図であ
る。グリツドがケース1の内面に設けるなら、グ
リツドを0電位つまりアースにすることでフオセ
ツト現象を除去できる。 FIG. 5 is a diagram showing the relationship between the distance between the grid and case 1 and the optimum grid bias voltage for zero correction. If the grid is provided on the inner surface of the case 1, the offset phenomenon can be eliminated by placing the grid at zero potential, that is, earth.
以上のように電位計の検出窓にグリツドを設
け、それにバイアス電圧を印加することで、オフ
セツト現象を除去し、実際の表面電位と検出電位
との相対関係を正確にできる。 By providing a grid in the detection window of the electrometer and applying a bias voltage to it as described above, the offset phenomenon can be removed and the relative relationship between the actual surface potential and the detected potential can be accurately determined.
第1−1図は電位計の平面図、第1−2図は電
位計の断面図、第1−3図は電位計の斜視図、第
2図は電位測定回路図、第3図は本発明による測
定グラフ図、第4図は従来の測定グラフ図、第5
図はバイアス電圧グラフ図であり、図中1は電位
計ケース、2は検出窓、4はグリツド、16はク
ランプ回路である。
Figure 1-1 is a plan view of the electrometer, Figure 1-2 is a cross-sectional view of the electrometer, Figure 1-3 is a perspective view of the electrometer, Figure 2 is a potential measurement circuit diagram, and Figure 3 is a bookmark. The measurement graph according to the invention, Fig. 4, is the conventional measurement graph, Fig. 5
The figure is a bias voltage graph, in which 1 is an electrometer case, 2 is a detection window, 4 is a grid, and 16 is a clamp circuit.
Claims (1)
グリツドを設け、そのグリツドに零または正ない
し負の所定電位を印加することによつて、オフセ
ツト現象を除去したことを特徴とする表面電位
計。1. A surface electrometer characterized in that an offset phenomenon is eliminated by providing a grid in the opening window for potential detection in a rotary electrometer and applying a predetermined potential of zero, positive or negative to the grid.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5242279A JPS55144555A (en) | 1979-04-27 | 1979-04-27 | Surface potentiometer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5242279A JPS55144555A (en) | 1979-04-27 | 1979-04-27 | Surface potentiometer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55144555A JPS55144555A (en) | 1980-11-11 |
JPS6148668B2 true JPS6148668B2 (en) | 1986-10-25 |
Family
ID=12914336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5242279A Granted JPS55144555A (en) | 1979-04-27 | 1979-04-27 | Surface potentiometer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55144555A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104502733B (en) * | 2014-12-26 | 2017-04-05 | 清华大学 | A kind of optical measuring system for DC electric field field strength measurement |
-
1979
- 1979-04-27 JP JP5242279A patent/JPS55144555A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS55144555A (en) | 1980-11-11 |
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