JPS6146986A - Display function expander - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a display system m+ for so-called character and graphic information services.
Concerning device function expansion.

[Background Art] A display control device for character and graphic information services generally consists of a raster surface for specifying a background color, a photographic surface for drawing a photograph, a geometric surface for specifying a figure, and a character surface for displaying kanji, etc. has been done. Of these, the geometric plane transmits display signals in bitmap mode (BMM), while the photographic plane and character plane transmit display signals in block color mode (BGM).

Here, the bitmap mode is a mode in which display signals are stored by matching the bit arrangement order on the video RAM with the display order on the CRT.

The block color mode is a mode in which 4 dots x 4 dots on a CRT constitute one block, and the display signals within that block are stored together.

In other words, the block color mode uses 16 bits as dot information bits, 4 bits each as foreground color bits and background color bits, and 2 bits as flash bits for each block. It is. Here, the dot information bit is a bit assigned to each of the 16 dots in one block. Further, the foreground color bit specifies the color to be given to the dot on the CRT whose dot information bit is "1", and the background color bit specifies the color to be given to the dot on the CRT whose dot information bit is "1". This specifies the color to be given to a dot on a CRT whose information pit is "0". Therefore, one byte consisting of 4 bits for the foreground color and 4 bits for the background color provides 16 dots of color information. Further, the flashing bit specifies whether or not a dot on the CRT should blink, or whether the blinking is in the normal phase or in the negative phase.

The reason why the display control device for character and graphic information services employs a block color mode, which is more special than the bitmap mode, is that it has the advantage that the absolute memory m is smaller.

That is, in the bitmap mode, to display one dot, a total of 6 bits, 4 dots for color designation and 2 pits for blinking, is required, and 96 bits are required to display 16 dots. On the other hand, when displaying 16 dots in block color mode, 2
6 bits (=16+4+4+2 bits) are sufficient.

[Problems with the Background Art] As described above, since the display control device for character and graphic information services is unique, there is a problem in that it would be extremely expensive if it were implemented as it is in hardware.

In other words, in order to receive a display signal in block color mode and display it in normal bitmap mode, the display control device for character and graphic information services must convert the block color mode to bitmap mode. Conversion is complicated. Therefore, there is a problem in that if the conversion is directly implemented using hardware, it will be extremely expensive.

[Object of the Invention] The present invention has been made by focusing on the problems of the prior art described above, and uses a normal bitmap type display control device to display a display signal transmitted in a block color mode. The object of the present invention is to provide a display function expansion device that can display a screen.

[Summary of the Invention] The present invention provides a display function expansion section in parallel with a CRT controller.

[Embodiments of the invention] FIG. 1 is a block diagram showing one embodiment of the present invention.

The CRT controller CC is a controller that controls display based on a normal bitmap method. The character section memory M1 stores character data, the photo surface circumference memory M2 stores photo data, and the geometry section memory M3 stores geometry data. These memories M1. M2.
M3 is called a video RAM (hereinafter referred to as rVRAMJ). The display function expansion unit 10 is an element that causes a CRT to display a display based on a display signal transmitted in block color mode.

In the figure, AD is an address signal, RAS is a row address select signal, WR is a write signal (a signal specifying read/write), RD7 to O are read/write data, GASO, CAS1 are memories M1, M2 . Column address select signal specifying read/write of M3,
CASX is a selection strobe signal for the I10 register, which will be described briefly, DLCLK is a dot clock, and VDS is a video data select signal that controls whether to output display data or specify a CPU time slot.

In addition, BLEO is a composite signal that performs blanking, CB
is the geometric surface display data bus, INT is 601
-1z signal, G is green primary color signal, R is red primary color signal, B is pull'- primary color signal, Ys is luminance signal,
dd is a decoder, and C8 is a chip select signal.

Here, the geometry display data (bitmap mode) is stored on display memory bus RD7-0JCRT controller CC1 color bus CB3-0, display function expansion unit 10
Head to CRT via . However, the character and photo display data (block color mode)
It goes to the CRT via only the display function extension section 10.

FIG. 2 is an explanatory diagram of the bitmap mode.
1(A) shows a CRT screen, and FIG. 1(B) shows VRAM mapping.

As shown in Figure 2 (A), for each dot on the CRT, from the top left, 0.1, 2°3...
...and number it. On VRAM, 4 bits are allocated to each dot, and 1 byte specifies the color of 2 dots, and those 4 bits are used to select 1 out of 16 colors.
I'm trying to choose a color.

FIG. 3 is an explanatory diagram of block color mode, (A
) shows a CRT screen, (B) shows VRAM mapping, (C) shows the contents of attribute bits, (D) shows an explanation of attribute operation, and (
E) shows the name on the screen.

As shown in FIG. 3(A), the dots are divided into four groups from the upper left to the right of the CRT, and this set of four dots arranged in the horizontal direction is called a sub-block. Then, from the top left of the CRT to the right, the subblocks are 0.1, 2.3
．． Number them as ・・・・・・・・・. On the VRAM, 2 bytes are allocated to each subblock, and 4 dots are displayed using 2 bytes. The breakdown of those 2 bytes is:
The pattern bits (dot information bits) are 4 bits, the attribute bits are 4 bits, the foreground color bits are 4 bits, and the background color bits are 4 bits.

The foreground color bit specifies the color to be given to a dot on the CRT whose pattern bit is "1" in the same subblock. Furthermore, the background color bit refers to a CRT whose pattern bit is rOJ in the same sub-block.
This specifies the color to be given to the upper dot.

Further, as shown in FIG. 3(C), among the attribute bits, bits 3.2 constitute a flash bit, bits 1. O constitutes a raster color designation bit. FIG. 3(D) shows the flash state or designated raster color when the value of each bit is changed. Here, the code FL is flash,
The symbol RA indicates raster. In other words, when a color in a certain sub-block is specified to be transparent, the rask color specification bit in that sub-block is set to, for example, “
00'' means that the bit is colored in the same color as the header coloring shown in FIG. 3(E).

FIG. 4 is a block diagram showing an example of a display function expansion section according to the present invention.

The control unit 20 has an I10 register consisting of an access plane select register, a mode register, and a palette address register, and has memories M1 and M2 (VRAM
) to control conversion from bitmap mode to block color mode as well as function expansion. The path buffer 20a takes in the signals of the display memory buses RD7 to RD0 to the character surface memory M1 when receiving an enable signal from the control section 20. The path buffer 20b is.

When an enable signal is received from the control section 20, the signals on the display memory buses RD7 to RD0 are taken into the photographic image memory M2.

Further, the character surface circumference color selector 31 (a specific example is shown in FIG. 6) performs parallel-to-serial conversion of bitmap mode signals and selects colors for block color mode signals. The character music bit conversion circuit 41 (details shown in FIG. 8-9) converts each G, R, and B into four bits based on the foreground color bit or background color bit in the block color mode.
- bit (12 bits in total) color code.

The color selector 32 for the photo section (a specific example is shown in FIG. 7) is similar to the color selector 31 for the character section, and the bit conversion circuit 42 is similar to the bit conversion circuit 41 for character music. be.

Color palette for geometric music 33. The raster surface color palette 34 is composed of a small number of registers (or RAM), and can specify a large number of color codes based on a normal lookup table (shown in FIG. 10). be. In the embodiment shown in FIG. 10, the color palette 33 for geometric music is as follows:
It is composed of 16 12-bit registers, and by writing 4-bit data into each of G, R, and B colors, it is possible to select 4000 color codes. The above-mentioned 7-dressing of 16 register writes is performed by auto-increment, and when rewriting the data, advance from an even address.

The raster surface color palette 34 is composed of four 12-bit registers, and by writing 4-bit data to each color of G, R, and B, 4000 You can select from the color code.

The priority selector 50 (a specific example is shown in FIG. 11) converts the block-colored signal of the character side, the converted block-colored signal of the photographic side, and the geometric side signal. , raster plane signals. Here, if the raster surface color palette 34 is selected,
This is a case where the display colors of the character surface, geometry surface, and photographic surface all represent transparency.

The transparent processing circuit 60 includes all "0" detection circuits 61, 62, 6 that detect that all 4-bit signals are "0".
The priority selector 50 and the selectors 71, 72, and 73 are operated based on the signals from 3.64 and the like. In addition, all "0" detection circuit 61.62
is composed of four OR circuits, all “0” detection path 6
3°64 is composed of 12 OR circuits.

Selectors 71, 72, and 73 are for selecting output in the bitmap mode and output in the block color mode.

FIG. 5 is an explanatory diagram of the control section, and (A) is a block diagram showing an example of the control section.

That is, as shown in FIG. 5(B), the access plane bits AP1. of the access plane select register 21 are selected.
APO is ro, OJ, ro, 1J.

Photographic surface for rl and OJ, respectively.

Geometric plane and character plane are specified.

Access Brenbit AP1. The output of APO is decoded by a decoder, and this signal is sent to CASO.

CASl and AND CASCO, CASCl or C
Create ASPO, CASPl. Then, depending on the decoder output and CASO, CASl, the path buffer 20
a, 20b, the direction and opening/closing control are performed.

In addition, as shown in FIG. 5(C), the mode register 22
If the display mode bit DM is "1" or "0", the bitmap mode is selected.

When the block color mode is selected and the ignosiametric blend bit IGP is rIJ or rOJ, respectively, [Do not display the color code of the geometric surface]
, [Also display color code of geometric surface] is selected. In addition, Evenoa Character Brempit IC
P is "1".

In the case of "0", "do not display the color code of the character side" and "display the color code of the character side" are selected, respectively.

Palette address bits PAO, PA1°PA2. of the palette address register 23 shown in FIG. 5(D). PA3
．． PA4. PA5 constitutes the address shown in FIG. If the address is O~1F (HEX), specify one of the registers of the geometric face color palette 33 (indicated simply as "palette" in FIG. 10). , if the address is 20 to 27 (HEX), the corresponding register is specified among the registers (indicated simply as "raster" in FIG. 10) of the raster plane color palette 34. A well-known lookup table may be used as a circuit configuring the "palette" or "raster".

FIG. 6 is a specific example of the character surface color selector.

The shift register 31a converts the 8-bit parallel signal from the character-heavy memory M1 into 4-bit serial signals (8 bits each).
MG3.8MG2.8MG1.8MGO)
It is sent to the selector 71 and is in bitmap mode (
This is for processing the signals of BMM). In other words,
In the bitmap mode, 2 bytes are divided into 4 bits each to control the display of 4 dots.

A block color mode (BCM) signal is processed by a shift register 31b that shifts one bit at a time, an attribute register 31G, a foreground color register 31d, a background color register 31e, and a selector 31f.

That is, first, 2 bytes of data from memory M1 are
It is sent to registers 31b, 31c, 31d, and 31e and held there. Then, the shift register 31b selects bit 7.
．． In the order of 6 and 5.4, the pattern bits are sent to the logic circuit one by one, and the attribute register 31c
is sending attribute bit 3.2 to the logic circuit.

The logic circuit sends the logic result to the control section of the selector 31f. On the other hand, foreground color register 3
1i outputs the color code of the pattern bit "1", the background color register 31d outputs the color code of the pattern bit "0", and these two types of color codes are selected by the selector 31f, It is sent to the bit conversion circuit 41.

In this way, when the color code regarding the four pattern bits is sent to the bit conversion circuit 41, the next two bytes are sent to the registers 31b, 31c, and 31d.

31e and held, and the same operation as above is performed.

Also, the 60Hz INT signal is converted to 1H by the frequency dividing circuit.
2 clock (see Figure 4), and this IH2 clock and the signal of attribute bit 3.2 are divided into
Theory F with logic circuits! ! (see FIG. 6), and in certain cases, the foreground color and background color are switched every 0.5 seconds. That is, when the signals of attribute bit 3.2 are ro, IJ, rl, and OJ, the foreground color and background color are switched in positive phase and negative phase, respectively. In this way, flash control is performed. Note that the above attribute bit 3.2 is a flash control attribute bit.

FIG. 7 is a block diagram showing a specific example of the color selector 32 for the photography section, and is a circuit similar to that in FIG. 6. The shift register 32a is similar to the shift register 31a, and converts the 8-bit parallel signal from the photographic memory M2 into 4-bit serial signals (8MR3°8MR2, BMR1, BMRO). , to the selector 72.

On the other hand, the above signals BMR3, BMR2, BMR1°BMR
Corresponding to O, the signal BMB3.8MB2°BMBl,B
The MBO is converted in the CRT controller CC1, C
It is sent to the selector 73 via the lines B3 to O.

FIG. 8 is a diagram without showing the bit conversion circuit for the character part.

The bit conversion circuit 41 converts a 4-bit color code into a 12-bit color code, and is composed of a ROM. That is, in block color mode, 1
For each dot, the color code generated by the color selector 31 is output as a 4-bit code for each of G, R, and B. Here, the codes CG, CR, and CB are, respectively,
It does not indicate that it is a G, R, B signal on the character side.

FIG. 9 is a diagram showing a color conversion table in the bit conversion circuit.

In FIG. 9, the input of the bit conversion circuit 41, its output, and color names are shown. Here, among the dark color output codes, "0110" is an example, but r
Other bit combinations such as o111J may also be used. CG, O
When both R and CB are "1111", the screen is displayed in white, and when both are rooolJ, the screen is displayed in black. Also, CG, CR, and CB are all r
'o.

00", it will be treated as transparent, and the display will be performed based on the color code specified in the next priority plane according to the priority order of character side, geometry side, photography side, and raster side. .

Note that the explanations regarding FIGS. 8 and 9 are similarly applied to the bit conversion circuit 42 around the photo surface.

FIG. 10 is an explanatory diagram of the color palette and raster.

In FIG. 10, the relationship between the addresses specified by bits 5 to 0 (palette address bits PA5 to PAO) of the palette address register 23 provided in the control unit 20 and the output color codes of the color palettes 33 and 34 is shown. It shows.

In other words, if the address specified by palette address bits PA5 to PAO is 0 to 1F (HEX), 8
The color code of the bit is sent to the geometric circumference color palette 33. A set of color codes is specified by the two bytes specified by the odd address and the next even address. Since bits 7 to 4 of even addresses are not used, only 12 bits of the 2 bytes are used as a color code. The contents of this 12-bit color code can be freely changed, so 16 colors can be selected from about 4000 colors.

Further, when the address specified by palette address bits PA5 to PAO is 20 to 27 (HEX), an 8-bit color code is sent to the raster surface color palette 34. A set of color codes is specified by the 12 bits specified by that odd number address and the next even number address,
This is the color code for headers, screens, messages, and buttons.

Incidentally, in FIG. 10, the blank portion is a portion whose display is omitted, and each bit is specified in the same manner as in the other portions.

FIG. 11 is a diagram showing a specific example of the priority selector.

The priority selector 50 includes selectors 51, 52.
53.54, 55.56, selector 51.5
2.53.54.55.56 each have a control section and a switching section. The control section includes an i selection signal PR31 generated in the transparent processing circuit 60.
, PR3O (signal PR8I has a weight of 2, signal PR
8O has a weight of 1>, and the switching section receives color codes from the character plane, photography plane, geometry plane, and raster plane and selects one code among them.

In addition, in FIG. 11, the priority selector 50
The first letters of the alphabet C, P, G, and R indicate character, photography, geometry, and raster, respectively, and the second letters of the alphabet G and R indicate input signals.

B represents green, red, and blue, respectively. Further, the third character number represents the weight. moreover,
Among the codes indicating the output signals of the priority selector 50, the first and second letters PS indicate the output signals of the priority selector 50, and the third letters G, R, and B indicate green, green, and B, respectively. Red.

Blue is shown, and the fourth character number represents the weight.

FIG. 12 is a diagram without showing a specific example of the transparent processing circuit.

This transparency processing circuit 60 detects that the color code applied to the character surface, photo/spiky graph surface, geometry surface, and raster surface indicates "transparent", and depending on the detection result, , priority selector 50
However, the color code of the surface located in the priority order next to the surface indicating 1 "transparent" is selected.

Note that the code CTR is character transparent, a signal indicating that the output of the character surface is transparent, and the code ICP is an even character plane, a signal specified by 1 bit of the mode register 22, and the code GT
R is geometry transparent, a signal indicating that the output of the geometry surface is transparent; symbol IGP is an even geometry cube;
Signal specified by 1 bit of register 22, code PTR
1 is a signal indicating that the output of the photographic surface is transparent,
The symbol RTR is a raster transparent signal, which is a signal indicating that the raster surface output is transparent.

Further, the transparency processing circuit 60 generates a control signal SBMM for selecting the output of the priority selector 50 when the bitmap mode is specified and the character side or the photographic side is not transparent. This control signal SB
MM is sent to selector 71.72.73. Also,
By using the control signal SBMM, the output of the color palette 33, 34 can be selected.

Note that the code DM is "1" in the display mode.
The symbol C0TR is a signal that outputs "1" when the all "0" detection circuit 61 detects all "0", and the symbol POTR is a signal that outputs "1" when the all "0" detection circuit 62 detects all "0". All ゛″0′.

This is a signal that outputs “1” when it detects, and the sign @B
LK is a signal that outputs "1" when blanking the screen.

FIG. 13 is a diagram showing a specific example of the selectors 71, 72, and 73.

When the 1-bit control signal 88MM is "1", selects the signal corresponding to the bitmap mode (the signal in which the two characters on the left are BM), and when it is "0", it corresponds to the block color mode. Select the signal (the signal with PS as the two characters on the left). G3 selected in this way
~Go, R3~R0, and 83~BO signals are, respectively.
The D/A converter 80 converts the signal into an analog signal.

In addition, in the case of bitmap mode, in order to realize a 12-page bitmap, the signal of the character picture memory M1, the signal of the photography part memory M2, and the signal of the geometry part memory M3 are sent to the green 4, respectively. surface,
It corresponds to 4 red sides and 4 blue sides.

Note that in the above embodiment, one block consists of 4 bits x 4 bits.
Although described as bits, it may also be m bits×n bits (m is an integer of 2 or more, and n is an integer of 1 or more). In this case, one block is divided into n nub blocks each consisting of m dots x 1 dot, and each subblock has a pattern bit consisting of m bits, a foreground color bit, and a background color bit. and attribute bits.

[Effects of the Invention] The present invention has the advantage that it is possible to display a screen based on display data transmitted in block color mode using a normal bitmap type display control device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the bitmap mode. (A) is the CR1 screen, (B)
is a diagram showing VRAM mapping, and Figure 3 is an explanatory diagram of block color mode, (A) is the CR1 screen, (B
) is VRAM mapping, (C) is the content of the attribute, (D) is an explanation of the operation of the attribute, (E) is a diagram showing the name on the screen, and Figure 4 is a block diagram showing an example of the display 11 function expansion part. , FIG. 5 is an explanatory diagram of the control section, (
A> is a control unit, (B) is an access brain select register, (C) is a mode register, (D) is a diagram showing a palette address register, FIG. 6 is a diagram showing a specific example of a character surface color selector, Figure 7 is a diagram showing a specific example of the color selector for the photography section, Figure 8 is a diagram that does not show the bit conversion circuit for character heavy use, Figure 9 is a diagram showing a single color conversion table in the bit conversion circuit, and Figure 10 is a diagram showing the color selector. 11 is a diagram showing a specific example of a priority selector, FIG. 12 is a diagram showing a specific example of a transparent processing circuit, and FIG. 13 is a diagram showing a specific example of a selector. 10... Display function extension section, 20... Control section, 31.
・・Character surface color selector, 32...F 1st
- Color selector for graph plane, 33... Color palette for geometric drawing, 34... Color palette for raster plane, 41.42... Bit conversion circuit, 50...
Priority selector, 60...transparent processing circuit, 7
1.72.73... Selector, Ml... Character music memory (VRAM), M2... Memory for photography section (VRAM), M3... Geometric surface circumference memory (VRAM). Patent applicant: ASCII Co., Ltd. Figure 2, Figure 3, Figure 5 (ADl, ACOI Figure 10)

Claims (5)

[Claims] (1) In a display control device for character and graphic information services, there is a bitmap mode in which display data is stored by matching the bit arrangement order on the video RAM with the display order on the CRT, and m dots x n on the CRT. One block consists of dots (m is an integer of 2 or more, n is an integer of 1 or more).
mode selection means for selecting one of block color modes in which display data is stored for each block; bitmap mode display means for displaying in the bitmap mode based on the mode selection means; and mode selection means for displaying in the bitmap mode. A display function expansion device comprising: block color mode display means for displaying in the block color mode based on; (2) The display signal of the block color mode, in which m dots x n dots (m is an integer of 2 or more, n is an integer of 1 or more) on a CRT, is defined as one block, and a display signal is transmitted for each block is m dots. A display function expansion device characterized in that the display function expansion device is divided into n sub-blocks each consisting of ×1 dot, and each sub-block is provided with a pattern bit consisting of m bits and an attribute bit. (3) The display function expansion device according to claim 2, wherein the attribute bits include a foreground color bit, a background color bit, and a flash control attribute bit. . (4) In claim 2, the m dots are 4 dots, and the n dots are 4 dots.
A display function expansion device characterized by being a dot. (5) In claim 1, the bitmap mode display means or block color mode display means is a color selector that performs parallel-to-serial conversion when in the bitmap mode and selects a color when in the block mode. A display function expansion device comprising: