JPS6145255B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pen-touch type input device, and more particularly to a pen-touch type input device in which a plurality of probes can be used for one tablet.

Conventionally, various types of pen-touch type input devices, such as photoelectric coupling, electromagnetic coupling, and capacitive coupling, have been proposed and put into practical use.

However, since the conventional keyboard type input device operates the keyboard with both hands, there is an intuitive concept that the input speed is faster than that of the conventional pen-touch type input device in which the probe is held and operated with one hand. However, in reality, even with conventional pen-touch type input devices, the input speed is 60 to 70 characters/minute or more, which is comparable to keyboard type input devices.

Therefore, it has been proposed to increase the input speed of the pen-touch type input device as compared to the conventional pen-touch type input device by allowing the user to carry out input operations by holding a probe in each hand.

The present invention provides a tablet that uses a plurality of probes, in which the signal detected by the probe is the detection signal of a specific probe according to a preset priority among the plurality of probes in contact with the tablet. This paper proposes a device to do this.

The present invention will be described in detail below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram showing the entirety of a pen-touch type input device using a capacitively coupled tablet as an embodiment. This configuration and operation will be schematically explained below. Inside the tablet 1, a plurality of conductors 2 arranged in the X-axis direction and a plurality of conductors 3 arranged in the Y-axis direction are arranged with a dielectric material 4 in between. Furthermore, a character sheet 5 on which characters, symbols, numbers, etc. are displayed on key segments is placed on the top surface of the tablet 1. A plurality of conductors 2 and 3 built into the tablet 1 are sequentially supplied with scanning pulses by a control circuit 7. The probe 8 or 9 that is in contact with the tablet 1 is capacitively coupled to the conductor to which the scanning pulse is supplied, and supplies the scanning pulse to the selection circuit 6 as a detection signal. This selection circuit 6 transfers the detected signal to the control circuit 7.
This control circuit 7 outputs to the outside a code corresponding to the position of the tablet in contact with the probe that detected the signal or the letters, symbols, numbers, etc. displayed on the character sheet 5 on the tablet 1. .

Next, the present invention will be specifically explained using the embodiment shown in FIG. A clock pulse generator 10 constantly supplies a clock pulse, for example a 1 MHz clock pulse, to a frequency divider 11. Frequency divider 11 divides the frequency of the clock pulse from pulse generator 10 and supplies the divided pulses to counter 12 and control circuit 27. Counter 12 is connected to one input terminal of switching circuit 13. The other input terminal of this switching circuit 13 is the OR gate 2 of the priority selection circuit 51.
0 output terminal. An output terminal of the switching circuit 13 is connected to an X-axis decoder 14 and a Y-axis decoder 15. The X-axis decoder 14 is connected to each conductor 2 in the X-axis direction, and the Y-axis decoder 1
5 is connected to each conductor 3 in the Y-axis direction. Signal detection lines 8b and 9b of probes 8 and 9 are connected to one input terminal of each AND gate 24 and 25 of selection circuit 32, respectively. On the other hand, switches 8 provided on probes 8 and 9 respectively
a and 9a are connected to one input terminal of each AND gate 16 and 17 of the priority selection circuit 51, respectively. The priority selection circuit 51 is a circuit for selecting the priority of probes, and includes three AND gates 16,
17, 19, three flip-flops (hereinafter simply referred to as FF) 21, 22, 23, inverter 1
8 and an or gate 20. The output terminal of the AND gate 16 of the priority selection circuit 51 is connected to the inverter 18, one input terminal of the OR gate 20, and the input terminal of the F.F 22. The output terminal of AND gate 17 is connected to one input terminal of AND gate 19, and the other input terminal of AND gate 19 is connected to the output terminal of inverter 18. The output terminal of the AND gate 19 is the other input terminal of the OR gate 20 and F.F23.
is connected to the input terminal of The output terminal of the OR gate 20 is the input terminal of F/F21, and the switching circuit 13
and the control circuit 27, respectively. The output terminal of F.F21 is connected to the other input terminal of AND gates 16 and 17. The selection circuit 52 is for supplying a signal from one of the two probes 8 and 9 to the control circuit 27, and has AND gates 24 and 25 and an OR gate 26. The output terminals of the AND gates 24 and 25 are each connected to the input terminal of an OR gate 26, and the output terminal of the OR gate 26 is connected to a control circuit 27. The output side of the control circuit 27 is connected to the reset terminals of the F.Fs 21, 22, and 23 and one input terminal of a gate circuit 28, and the other input terminal of the gate circuit 28 is connected to a register 29.

Next, the operation of this embodiment will be explained. The counter 12 is a clock pulse generator 1 from the frequency divider 11.
It is incremented by a pulse obtained by dividing a clock pulse of 0, and its count contents are always supplied to the gate circuit 28. Now, when the probe 8 is brought into contact with an arbitrary position of the tablet 1, for example, the positions Xi and Yj,
A switch 8a provided on the probe 8 is energized and turned ON, and a power supply voltage is supplied to the AND gate 16 of the priority selection circuit 51 via the switch 8a from an appropriate power source (not shown). At this time F.F.
Since 21 is in standby state, the output is AND gate 1
It is supplied to input terminals 6 and 17. The AND gate 16 then operates and supplies a signal to the inverter 18, the OR gate 20, and the F.F 22. Since the output signal of the AND gate 16 is inverted by the inverter 18, no signal is supplied to one input terminal of the AND gate 19. Therefore, even if the probe 9 is brought into contact after the probe 8 is brought into contact, the AND gate 19 will not operate. Further, since the F.F.21 to which the input signal is supplied is inverted and its output disappears, the AND gates 16 and 17 will not operate even if the probes 8 and 9 come into contact unless the F.F.21 is reset. The switching circuit 13 supplied with the output signal of the OR gate 20 sequentially scans the X-axis decoder 14 and the Y-axis decoder 15 individually and sequentially applies the pulses from the counter 12 to the conductors 2 and 3 in the X- and Y-axis directions. supply Here, X
When a scanning pulse is supplied to the i-th conductor of the conductor 2 in the axial direction, the probe 8 and the i-th conductor of the conductor 2 in the X-axis direction
The probe 8 is capacitively coupled to the th conductor, and a scanning pulse is supplied from the probe 8 to one input terminal of the AND gate 24 of the selection circuit 52 through the signal line 8b. Since the other input terminal of the AND gate 22 is supplied with the Q signal of the F.F 22, the signal detected by the probe 8 is used to supply a signal to the OR gate 26.
The output of this OR gate 26 is supplied to a control circuit 27. This control circuit 27 supplies the signal from the OR gate 26 to the gate circuit 28 in response to the synchronization pulse from the frequency divider 11. Since the count state of the counter 12 (representing i in this case) is always supplied to the other input terminal, the gate circuit 28 registers the count contents of the counter 12 in synchronization with the signal from the control circuit 27. Supply to 29. This register 29 latches the count contents of the counter 12 until an output command signal is supplied from a suitable external device (not shown). Counter 1 corresponding to the X-axis direction position (Xi) of probe 8
When the count contents of 2 are latched in the register 29, the output pulses of the switching circuit 13 are sequentially supplied to the Y-axis conductor 3 via the Y-axis decoder 15. Hereinafter, the tablet 1 which is in contact with the probe 8 operates in the Y-axis direction in the same manner as in the X-axis direction.
counter 12 corresponding to the Y-direction position (Yj) of
The count contents are latched in the register 29.
Here, the signal latched in the register 29 as a signal corresponding to the position (Xi, Yj) of the probe 8 in contact with the tablet 1 is outputted to the outside by the aforementioned output command signal.

In addition, in order to improve the detection accuracy of the detection position,
It is also possible to perform detection multiple times in each direction and output when the respective signals match. Furthermore, the signal supplied to the control circuit 27 among the outputs of the OR gate 20 operates as an initial reset of the control circuit 27. Further, the control circuit 27 sends the reset signal of the F/F 21 to the register 29 using the output command signal.
is supplied after outputting the signal to the outside.

Next, the case where the probe 9 is brought into contact with the tablet 1 will be explained. When the probe 9 is brought into contact with the tablet 1, the switch 9a is turned on and power supply voltage is supplied to the AND gate 17 from an appropriate power source (not shown) via the switch 9a. At this time,
AND gate 17 supplies a signal to AND gate 19 since F.F 21 is in the reset state.
In addition, since the probe 8 is not in contact with the tablet 1 and is free, the AND gate 16 does not output a signal and the inverter 18 supplies the signal to the AND gate 19, which in turn supplies the signal to the OR gate 20 and F・Supply to F23. After this, the same operation as when the probe 8 is brought into contact is performed, and a signal corresponding to the position of the tablet 1 where the probe 9 is brought into contact is output.

In this embodiment, the AND gates 16, 1
7. The inverter 18, AND gate 19, OR gate 20, and F/F 21 always detect only one probe's signal, and if both probes are brought into contact at the same time (actually, this device does not use ), which is almost impossible considering the frequency of the clock pulse.), only the circuit corresponding to the probe 8 operates, so no erroneous signal is output. In this embodiment, the case where there are two probes has been described, but it is also possible to use three or more probes and set priorities for each probe.

Next, as another embodiment of the priority selection circuit, an example will be described with reference to FIG. 3 in which, in addition to the priority order of the probes, priority is also given to the reset when each probe is contacted successively. The same components as in FIGS. 1 and 2 are given the same reference numerals.

A switch 8a provided on the probe 8, a switch 9a provided on the probe 9, and a switch Xa provided on the third probe X are connected to F*Fs 30, 31, and 32 of the priority selection circuit 53, respectively. The output terminals of these F/Fs 30, 31, and 32 are AND gates 33, 34, and 35, respectively.
is connected to one input terminal of the The output terminals of the AND gates 33, 34, and 35 are connected to the input terminal of a decoder 36. The input terminal ²⁰ of the decoder 36 is connected to an AND gate 33, the input terminal ²¹ is connected to an AND gate 34, and the output terminal ²² of an AND gate 35 is connected, respectively. Decoder 3
A monostable multivibrator (hereinafter simply referred to as MM) 39 and an inverter 48 are connected to the output terminal 0 of the decoder 36, and output terminals 1, 3, 5 of the decoder 36,
7 is connected to an OR gate 37, output terminals 2 and 6 of the decoder 36 are connected to an OR gate 38, and output terminal 4 of the decoder 36 is connected to a data latch circuit 40, respectively. The output terminal of the inverter 48 is F/F47
The input terminal of the OR gate 37 is connected to the A terminal of the latch circuit 40, the output terminal of the OR gate 38 is connected to the B terminal of the latch circuit 40, and the output terminal 4 of the decoder 36 is connected to the C terminal of the latch circuit 40. . The output terminal of MM39 is latch circuit 4
Connected to the 0 latch terminal. Latch circuit 4
The output terminal QA of 0 is connected to one input terminal of each of the AND gate 41 and the AND gate 44 of the selection circuit 54. The output terminal QB of the latch circuit 40 is connected to one input terminal of each of the AND gate 42 and the AND gate 45 of the selection circuit 54. Furthermore, the output terminal QC of the latch circuit 40
are connected to one input terminal of each of the AND gate 43 and the AND gate 46 of the selection circuit 54. The other input terminals of the AND gates 41, 42, and 43 are connected to the Q output terminal of the F.F. 47, and the output terminals of the AND gates 41, 42, and 43 are connected to the reset terminal R of the F.F. It is connected to the. and gate 44,4
The other input terminals of probes 5 and 46 are connected to probes 8, 9, and X, respectively. and gate 4
The output terminals 4, 45, and 46 are connected to the input terminal of the OR gate 26 of the selection circuit 54. The output terminal of the F.F47 is an AND gate 33,3
It is connected to the other input terminal of 4 and 35.

Next, the operation of this embodiment will be explained. When none of probes 8, 9, and X are being operated,
Since the output signal of the control circuit 27 is negative, one of the input terminals of each of the AND gates 33, 34, and 35 has an F.
The output signal of F47 is supplied. Here, to explain the case where the probes 8 and 9 are brought into contact with the tablet 1 at the same time, the switches 8a and 9a provided on the probes 8 and 9 are turned on, and the switches F and F30 and F3 are turned on.
1 is triggered and reversed, Q of F・F30,31
The outputs are supplied to one input terminal of AND gates 33 and 34, respectively. As mentioned above, FF・4
7 also supplies the signal to the other input terminals of the AND gates 33 and 34, so the AND gates 33 and 34 supply the signal to the decoder 36.

To explain the decoder 36 in detail, the input terminals 2 ⁰ , 2 ¹ , 2 ² are connected to the switches 8 a and 2 2 , respectively.
Compatible with 9a, Xa, switch 8a, 9
If both a and Xa are OFF, F・F3
0, 31, 32 do not work, so AND gate 3
3, 34, and 35 do not output signals, and only output terminal 0 of the decoder 36 supplies a signal to the MM 39. Depending on the operation status of switches 8a, 9a, and Xa, the decoder 36 outputs a signal to the output terminal as a normal binary number, and switch 8a is ON.
In the case of odd number of output terminals, i.e. 1, 3, 5, 7
A signal appears on one of the switches, and switch 9a turns on.
In the case of , the output signal appears on either 2, 3, 6, or 7, and when switch Xa is ON, the output signal appears on 4, 5, or 7.
The output signal appears on either 6 or 7. Therefore, in this embodiment, in order to set the priority order of the probes, when the probe 8 comes into contact with the tablet 1, the output terminals 1, 3,
When a signal appears on either terminal 5 or 7, or when probe 9 is brought into contact with tablet 1, when a signal appears on either output terminal 2 or 6 of decoder 36. , when the probe X comes into contact with the tablet 1, the output terminal 4 of the decoder 36
The structure is such that when a signal appears on

As described above, when signals are supplied from the AND gates 33 and 34 to the input terminals 2 ⁰ and 2 ¹ of the decoder 36 , the output terminal 3 of the decoder 36 supplies the signal to the OR gate 37 . or gate 3
The output signal of 7 is supplied to input terminal A of latch circuit 40. MM39 is output terminal 0 of decoder 36
The latch timing of the latch circuit 40 is controlled by the fall of the signal from the latch circuit 40. That is, by outputting a signal from an output terminal other than the 0 terminal of the decoder 36, the MM 39 causes the latch circuit 40 to perform a latch operation and output a signal corresponding to the input of the latch circuit 40. Since the signal is input to the input terminal A of the latch circuit 40, an output appears at the output terminal QA of the latch circuit 40, and the signal is supplied to one input terminal of each of the AND gates 41 and 44. Since the other input terminal of the AND gate 44 is connected to the probe 8, while a signal is being supplied from the output terminal QA of the latch circuit 40, the probe 8 is capacitively coupled to the conductors 2 and 3. The pulses supplied to each of the gates 3 and 3 are supplied to the input terminal of the OR gate 26. Thereafter, the operation explained in FIG. 2 is carried out, and a signal corresponding to the position of the tablet with which the probe 8 is brought into contact is outputted to the outside.

When the above operation is completed, a reset signal is supplied from the control circuit 27 to the reset terminal of F.F.47, and the signal of F.F.47 is applied to the AND gates 41 and 4.
2 and 43, respectively. Since a signal is supplied from the output terminal QA of the data latch circuit 40 to one input terminal of the AND gate 41, the AND gate 41 supplies a signal to the reset terminal R of the F.F.30 to reset the F.F.30. At the same time, the output signal of the AND gate 33 also disappears. When the probes 8a and 9a are further brought into contact with the tablet, the F.F.30 is not inverted and only the F.F.31 maintains the signal output state, and supplies the signal to the AND gate 34.
A signal is supplied to the input terminal 21 of the decoder 36 from the output terminal of the decoder 36 . The decoder 36 has the above-described configuration so that an output appears at the output terminal 2 and a signal is supplied to the OR gate 38. At this time, since there is no output from the output terminal O of the decoder 36, the F/F 47 is inverted by the output signal of the inverter 48. A latch circuit 40, whose input terminal B is supplied with a signal from the output terminal of the OR gate 38, supplies a signal to AND gates 42 and 45 from its output terminal QB. Since the probe 9 is connected to the other input terminal of the AND gate 45, the AND gate 45 is capacitively coupled to the conductors 2 and 3 of the tablet that the probe 9 is in contact with, as in the case of the probe 8. Conductor 2, 3
The pulses supplied to the gates are respectively supplied to the OR gate 26. Thereafter, it operates in the same manner as the probe 8, and sends out a signal corresponding to the position where the probe 9 on the tablet is brought into contact. When the above operations are completed, a reset signal is supplied from the control circuit 27 to the F*F 47, and the signal of the F*F 47 is supplied to the other input terminal of each of the AND gates 41, 42, and 43. Since a signal is supplied from the output terminal QB of the latch circuit 40 to one input terminal of the AND gate 42, the AND gate 42 supplies a signal to the reset terminal R of the F.F.31 to reset the F.F.31.

The above explanation is based on the case where two probes are brought into contact, but due to the priority setting of the decoder 36, even if probes 8, 9, and X are brought into contact with the tablet at the same time, the order of 8, 9, and Detection signals can be input sequentially. Although the case of two probes is illustrated in FIG. 2 and the case of three probes is illustrated in FIG. 3, the present invention is not limited to these examples. This can be implemented by changing the circuit configuration, or there is no problem even if other elements are used as the priority selection circuit.

As described above, in a tablet using a plurality of probes, the signals detected by the probes are sequentially scanned by the plurality of probes in contact with each other according to a preset priority order. Detection signals can be sequentially output as output signals, and it is also possible to improve input speed and prevent erroneous input.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the entire embodiment of the present invention, FIG. 2 is a block diagram showing the circuit, and FIG. 3 is a block diagram showing another embodiment of the priority selection circuit and selection circuit. . 1... Tablet; 2, 3... Conductor; 8, 9,
X... Probe; 8a, 9a, Xa... Switch; 16, 17, 19, 24, 25, 33, 3
4, 35, 41, 42, 43, 44, 45, 46
...and gate; 20, 26, 37, 38...
Or gate; 21, 22, 23, 30, 31, 3
2, 47...flip-flop; 36...decoder; 39...monostable multivibrator; 40
...Latch circuit; 18, 48, ...Inverter;
51, 53... Priority selection circuit; 52, 54... Selection circuit.

Claims (1)

[Scope of Claims] 1. A tablet having a plurality of key segments on its surface, a plurality of probes for indicating arbitrary key segments on the tablet, a switch provided on each of the plurality of probes, and a switch for each of the plurality of probes. a priority selection circuit that selects an output according to a preset arbitrary priority order; and a probe that corresponds to the output signal of the switch selected by the priority selection circuit from among the signals detected by the plurality of probes. 1. A pen-touch type input device comprising: a selection circuit that outputs a detection signal of as a position signal. 2. The pentouch type input device according to claim 1, wherein the priority selection circuit includes a reset circuit for resetting according to the priority order based on the output from the selection circuit.